From a662618c211e8a1d831377dcfab95f6a378aec52 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Tue, 28 Jul 2026 16:15:55 +0000 Subject: [PATCH 1/3] Update scalafmt-core to 3.11.5 --- .scalafmt.conf | 2 +- docs/getting-started/hello-world/scala-project/.scalafmt.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.scalafmt.conf b/.scalafmt.conf index 9af6c6cea..6fe120c16 100755 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.11.4 +version = 3.11.5 runner.dialect = scala3 maxColumn = 100 diff --git a/docs/getting-started/hello-world/scala-project/.scalafmt.conf b/docs/getting-started/hello-world/scala-project/.scalafmt.conf index 8cb1386e6..a77644948 100644 --- a/docs/getting-started/hello-world/scala-project/.scalafmt.conf +++ b/docs/getting-started/hello-world/scala-project/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.11.4 +version = 3.11.5 runner.dialect = scala3 maxColumn = 100 From c844b15c03f65edc560a86e2fcd412d3cda62461 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Tue, 28 Jul 2026 16:16:30 +0000 Subject: [PATCH 2/3] Reformat with scalafmt 3.11.5 Executed command: scalafmt --non-interactive --- .../main/scala/dfhdl/compiler/printing/DFValPrinter.scala | 2 +- .../stages/src/main/scala/dfhdl/sim/Interpreter.scala | 3 ++- compiler/stages/src/main/scala/dfhdl/sim/SimKernel.scala | 4 ++-- .../src/test/scala/dfhdl/sim/CompositeDesigns.scala | 6 +++--- .../main/scala/dfhdl/tools/toolsCore/DFToolsImage.scala | 8 ++++---- plugin/src/main/scala/plugin/MethodsPhase.scala | 8 ++++++-- 6 files changed, 18 insertions(+), 13 deletions(-) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFValPrinter.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFValPrinter.scala index 7b0aac937..b3e44ba5c 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFValPrinter.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFValPrinter.scala @@ -173,7 +173,7 @@ trait AbstractValPrinter extends AbstractPrinter: members.count { case dcl: DFVal.Dcl => !dcl.isPhantom && - (dcl.isPortIn || (dcl.isPortOut && !returnPort.contains(dcl))) + (dcl.isPortIn || (dcl.isPortOut && !returnPort.contains(dcl))) case _ => false } getSet.designDB.rootDB.subDBs.get(design.ownerRef) match diff --git a/compiler/stages/src/main/scala/dfhdl/sim/Interpreter.scala b/compiler/stages/src/main/scala/dfhdl/sim/Interpreter.scala index 3a37f2c84..e6ebad0de 100644 --- a/compiler/stages/src/main/scala/dfhdl/sim/Interpreter.scala +++ b/compiler/stages/src/main/scala/dfhdl/sim/Interpreter.scala @@ -58,7 +58,8 @@ object Interpreter: private val commitTmp = new Array[Long](regOut.length) // kernel-owned memory backing store: one long per word (masked at write). Reads (Op.MEMRD) // observe the pre-commit contents; write ports apply after the sweep, like registers. - private val mem: Array[Array[Long]] = Array.tabulate(memDepth.length)(k => new Array[Long](memDepth(k))) + private val mem: Array[Array[Long]] = + Array.tabulate(memDepth.length)(k => new Array[Long](memDepth(k))) // memory-less designs skip the commit entirely: a final-false branch the JIT folds out, so the // per-cycle path is identical to before the memory node existed (no added call or loop) private val hasMem = memWrites.length > 0 diff --git a/compiler/stages/src/main/scala/dfhdl/sim/SimKernel.scala b/compiler/stages/src/main/scala/dfhdl/sim/SimKernel.scala index 13cb463a3..59c5ed94e 100644 --- a/compiler/stages/src/main/scala/dfhdl/sim/SimKernel.scala +++ b/compiler/stages/src/main/scala/dfhdl/sim/SimKernel.scala @@ -8,8 +8,8 @@ package dfhdl.sim */ trait SimKernel: /** Install the reset image of each memory (indexed by memory id) into the kernel's backing store. - * Called once after construction; memory-less kernels ignore it. The kernel owns the working copy - * that writes mutate; `mems` is the reset image and is not retained. + * Called once after construction; memory-less kernels ignore it. The kernel owns the working + * copy that writes mutate; `mems` is the reset image and is not retained. */ def initMem(mems: Array[Array[Long]]): Unit = () diff --git a/compiler/stages/src/test/scala/dfhdl/sim/CompositeDesigns.scala b/compiler/stages/src/test/scala/dfhdl/sim/CompositeDesigns.scala index 64c15e6bd..2f3db9b98 100644 --- a/compiler/stages/src/test/scala/dfhdl/sim/CompositeDesigns.scala +++ b/compiler/stages/src/test/scala/dfhdl/sim/CompositeDesigns.scala @@ -65,9 +65,9 @@ class RegFileDut extends RTDesign: rdata := regs(raddr) end RegFileDut -/** Byte-enable RAM (the Servant firmware-RAM shape): 32-bit words with per-byte write enables - * (each a masked sub-cell write to the same dynamic address) plus a dynamic-index async read. - * Exercises the memory node's masked partial writes and read-first semantics on both tiers. +/** Byte-enable RAM (the Servant firmware-RAM shape): 32-bit words with per-byte write enables (each + * a masked sub-cell write to the same dynamic address) plus a dynamic-index async read. Exercises + * the memory node's masked partial writes and read-first semantics on both tiers. */ class ByteMemDut extends RTDesign: val waddr = UInt(3) <> IN diff --git a/lib/src/main/scala/dfhdl/tools/toolsCore/DFToolsImage.scala b/lib/src/main/scala/dfhdl/tools/toolsCore/DFToolsImage.scala index 93ed43090..c84ed83f7 100644 --- a/lib/src/main/scala/dfhdl/tools/toolsCore/DFToolsImage.scala +++ b/lib/src/main/scala/dfhdl/tools/toolsCore/DFToolsImage.scala @@ -153,10 +153,10 @@ object DFToolsImage: ) /** Whether the given image is resolvable (present locally / overridden / downloadable). A resolve - * failure (no container runtime, blocked unprivileged user namespaces, a corrupt or absent asset) - * is reported before returning false, so it is distinguishable from an image that is simply not - * configured — otherwise the only downstream symptom is a misleading "could not be found in its - * DFTools image". + * failure (no container runtime, blocked unprivileged user namespaces, a corrupt or absent + * asset) is reported before returning false, so it is distinguishable from an image that is + * simply not configured — otherwise the only downstream symptom is a misleading "could not be + * found in its DFTools image". */ def isAvailable(image: String): Boolean = try handle(image).exists diff --git a/plugin/src/main/scala/plugin/MethodsPhase.scala b/plugin/src/main/scala/plugin/MethodsPhase.scala index 1d3c4430d..28fa84224 100644 --- a/plugin/src/main/scala/plugin/MethodsPhase.scala +++ b/plugin/src/main/scala/plugin/MethodsPhase.scala @@ -181,6 +181,7 @@ class MethodsPhase(setting: Setting) extends CapturePhase: ) hasHDLMethodErrors = true } + end if if (isStatic) // The inverse of the ED rule: a static function is a region in which every value is // constant, so a non-constant argument has no meaning in it. Its const args become @@ -210,7 +211,10 @@ class MethodsPhase(setting: Setting) extends CapturePhase: // those parameter symbols are exempt from the "no `:==` in an ED method" body rule val nbArgSyms = dfValArgs.view.filter(_.tpt.tpe.isDFPortOUTNB).map(_.symbol).toSet checkHDLMethodContent( - anonDef, isStatic, isEDMethod && hasUnitRet(anonDef), nbArgSyms + anonDef, + isStatic, + isEDMethod && hasUnitRet(anonDef), + nbArgSyms ) { (msg, pos) => report.error(msg, pos) @@ -459,7 +463,7 @@ class MethodsPhase(setting: Setting) extends CapturePhase: // sits several `Apply`/`TypeApply` layers down the curried `:==` spine (extension // receiver, then rhs, then `using DFC`), so gather every argument along the spine. def spineArgs(t: Tree): List[Tree] = t match - case Apply(fun, as) => as ++ spineArgs(fun) + case Apply(fun, as) => as ++ spineArgs(fun) case TypeApply(fun, _) => spineArgs(fun) case _ => Nil val targetsNBArg = spineArgs(ap).exists(a => nbArgSyms.contains(a.symbol)) From f61f0555f3799b33e6fffce099a9964759b899c4 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Tue, 28 Jul 2026 16:16:30 +0000 Subject: [PATCH 3/3] Add 'Reformat with scalafmt 3.11.5' to .git-blame-ignore-revs --- .git-blame-ignore-revs | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .git-blame-ignore-revs diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs new file mode 100644 index 000000000..db0cbf5de --- /dev/null +++ b/.git-blame-ignore-revs @@ -0,0 +1,2 @@ +# Scala Steward: Reformat with scalafmt 3.11.5 +c844b15c03f65edc560a86e2fcd412d3cda62461