From bb093a1c10fde4aaffc56bb7c19e013893b6a4de Mon Sep 17 00:00:00 2001 From: ackPeng <1143590135@qq.com> Date: Wed, 22 Apr 2026 11:13:34 +0800 Subject: [PATCH 01/32] change recomputer rk35xx fan speed --- .../rk3576-recomputer-rk3576-devkit.dts | 16 ++++++++++------ .../rk3588-recomputer-rk3588-devkit.dts | 19 +++++++++++-------- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts b/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts index 28afce0731f7a..5b2f6638c9ea5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts @@ -42,7 +42,7 @@ status = "okay"; compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-levels = <0 50 100 150 200 255>; + cooling-levels = <25 45 60 75 100 130 170 210 255>; fan-supply = <&vcc_sys>; pwms = <&pwm0_2ch_0 0 60000 0>; @@ -53,10 +53,14 @@ pinctrl-0 = <&fan_tach>; rockchip,temp-trips = < - 20000 1 - 25000 2 - 30000 3 - 35000 5 + 38000 1 + 44000 2 + 50000 3 + 56000 4 + 62000 5 + 68000 6 + 74000 7 + 80000 8 >; }; @@ -758,7 +762,7 @@ interrupt-controller; gpio-line-names = "MIPI_DPHY_CSI0_IO1" ,"USB_USB30_PWREN_H", - "USB_HOST_PWREN_H" ,"PCIe_SX1261_RST_3V3", + "USB_HOST_PWREN_H" ,"BRD_ID_WP", "LTE_RESET" ,"P05", "P06" ,"LoRaWan_sx1262_CS", "USER_LED_R" ,"USER_LED_B", diff --git a/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts b/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts index 4862cc7472161..70491bb9d2b69 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts @@ -205,7 +205,7 @@ compatible = "pwm-fan"; #cooling-cells = <2>; pwms = <&pwm2 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; + cooling-levels = <25 45 60 75 100 130 170 210 255>; // cooling-levels = <0 255>; interrupt-parent = <&gpio3>; @@ -219,12 +219,15 @@ // >; rockchip,temp-trips = < - 40000 1 - 45000 2 - 50000 3 - 55000 4 - 60000 5 - >; + 38000 1 + 44000 2 + 50000 3 + 56000 4 + 62000 5 + 68000 6 + 74000 7 + 80000 8 + >; status = "okay"; }; @@ -378,7 +381,7 @@ &sdio { - max-frequency = <150000000>; + max-frequency = <100000000>; supports-sdio; bus-width = <4>; disable-wp; From 595659d00f80be326c0a34df4d3d24946028e561 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sat, 16 May 2026 09:44:44 +0200 Subject: [PATCH 02/32] drivers: char: drop "meko: vk2c21 LCD driver for the R58X-PRO" - this never worked, except for `123456` display on boot - was always built-in (not a module, and =y always) - This reverts commit 5e1407835d61ddec745744dcc197a4dbde5b562d --- drivers/char/Makefile | 2 - drivers/char/lcd_vk2c21.c | 707 -------------------------------------- drivers/char/lcd_vk2c21.h | 63 ---- 3 files changed, 772 deletions(-) delete mode 100644 drivers/char/lcd_vk2c21.c delete mode 100644 drivers/char/lcd_vk2c21.h diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 10b862fecd597..1b35d1724565e 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -45,5 +45,3 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o -#fox.luo@add vk2c21 lcd driver -obj-y += lcd_vk2c21.o diff --git a/drivers/char/lcd_vk2c21.c b/drivers/char/lcd_vk2c21.c deleted file mode 100644 index 0afde806a38d2..0000000000000 --- a/drivers/char/lcd_vk2c21.c +++ /dev/null @@ -1,707 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define LCD_EXT_DEBUG_INFO -#ifdef LCD_EXT_DEBUG_INFO -#define DBG_PRINT(...) printk(__VA_ARGS__) -#else -#define DBG_PRINT(...) -#endif -#define DEVICE_NAME "lcd_vk2c21" -/* ioctrl magic set */ -#define CH455_IOC_MAGIC 'h' -#define IOCTL_CHAR_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x10, unsigned char) -#define IOCTL_DOT_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x11, unsigned char) -#define IOCTL_COLON_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x12, unsigned char) -#define IOCTL_PWR_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x13, unsigned char) -#define IOCTL_LAN_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x14, unsigned char) -#define IOCTL_LAN_OFF _IOWR(CH455_IOC_MAGIC, 0x15, unsigned char) -#define IOCTL_WIFI_LOW_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x16, unsigned char) -#define IOCTL_WIFI_FINE_DISPLAY _IOWR(CH455_IOC_MAGIC, 0x17, unsigned char) -#define IOCTL_WIFI_OFF _IOWR(CH455_IOC_MAGIC, 0x18, unsigned char) -#define IOCTL_LED_ON _IOWR(CH455_IOC_MAGIC, 0x19, unsigned char) -#define IOCTL_LED_OFF _IOWR(CH455_IOC_MAGIC, 0x1a, unsigned char) - -//以下管脚输出定义根据客户单片机做相应的修改 -#define Vk2c21_SCL_H() gpio_set_value(gpio_i2c_scl,1) -#define Vk2c21_SCL_L() gpio_set_value(gpio_i2c_scl,0) - -#define Vk2c21_SDA_H() gpio_set_value(gpio_i2c_sda,1) -#define Vk2c21_SDA_L() gpio_set_value(gpio_i2c_sda,0) - -#define Vk2c21_GET_SDA() gpio_get_value(gpio_i2c_sda) -#define Vk2c21_SET_SDA_IN() gpio_direction_input(gpio_i2c_sda) -#define Vk2c21_SET_SDA_OUT() gpio_direction_output(gpio_i2c_sda, 1) - -static int gpio_i2c_scl,gpio_i2c_sda; -/** -****************************************************************************** -* @file vk2c21.c -* @author kevin_guo -* @version V1.2 -* @date 05-17-2020 -* @brief This file contains all the vk2c21 functions. -* 此文件适用于 VK2c21 -****************************************************************************** -* @attention -****************************************************************************** -*/ -#include "lcd_vk2c21.h" - -#define VK2c21_CLK 100 //SCL信号线频率,由delay_nus实现 50->10kHz 10->50kHz 5->100kHz -//驱动seg数 -//4com -//VK2C21A/B/C/D -#define Vk2c21_SEGNUM 13 -#define Vk2c21A_MAXSEGNUM 20 -#define Vk2c21B_MAXSEGNUM 16 -#define Vk2c21C_MAXSEGNUM 12 -#define Vk2c21D_MAXSEGNUM 8 - -//segtab[]数组对应实际的芯片到LCD连线，连线见-VK2c21参考电路 -//4com -//Vk2c21A -unsigned char vk2c21_segtab[Vk2c21_SEGNUM]={ - 18,17,16,15,14,13,12,11,10, - 9,8,7,6 -}; - -//4com -unsigned char vk2c21_dispram[Vk2c21_SEGNUM/2];//4COM时每个字节数据对应2个SEG -//8com -//unsigned char vk2c21_dispram[Vk2c21_SEGNUM];//8COM时每个字节数据对应1个SEG - -unsigned char shuzi_zimo[15]= //数字和字符字模 -{ - //0 1 2 3 4 5 6 7 8 9 - L o H i - 0xf5,0x05,0xb6,0x97,0x47,0xd3,0xf3,0x85,0xf7,0xd7,0x02,0x70,0x33,0x67,0x50 -}; -unsigned char vk2c21_segi,vk2c21_comi; -unsigned char vk2c21_maxcom;//驱动的com数VK2C23A可以是4com或者8com -unsigned char vk2c21_maxseg;//Vk2c21A=20 Vk2c21B=16 Vk2c21C=12 Vk2c21D=8 -/* Private function prototypes -----------------------------------------------*/ -unsigned char Vk2c21_InitSequence(void); -/* Private function ----------------------------------------------------------*/ - - -/******************************************************************************* -* Function Name : delay_nus -* Description : 延时1uS程序 -* Input : n->延时时间nuS -* Output : None -* Return : None -*******************************************************************************/ -static void delay_nus(unsigned int n) -{ - ndelay(n); -} -/******************************************************************************* -* Function Name : I2CStart I2CStop I2CSlaveAck -* I2CStart Description : 时钟线高时，数据线由高到低的跳变，表示I2C开始信号 -* I2CStop Description : 时钟线高时，数据线由低到高的跳变，表示I2C停止信号 -* I2CSlaveAck Description : I2C从机设备应答查询 -*******************************************************************************/ -static void Vk2c21_I2CStart( void ) -{ - Vk2c21_SCL_H(); - Vk2c21_SDA_H(); - delay_nus(VK2c21_CLK); - Vk2c21_SDA_L(); - delay_nus(VK2c21_CLK); -} - -static void Vk2c21_I2CStop( void ) -{ - Vk2c21_SCL_H(); - Vk2c21_SDA_L(); - delay_nus(VK2c21_CLK); - Vk2c21_SDA_H(); - delay_nus(VK2c21_CLK); -} - -static unsigned char Vk2c21_I2CSlaveAck( void ) -{ - unsigned int TimeOut; - unsigned char RetValue; - - Vk2c21_SCL_L(); - //单片机SDA脚为单向IO要设为输入脚 - Vk2c21_SET_SDA_IN(); - delay_nus(VK2c21_CLK); - Vk2c21_SCL_H();//第9个sclk上升沿 - - TimeOut = 10000; - while( TimeOut-- > 0 ) - { - if( Vk2c21_GET_SDA()!=0 )//读取ack - { - RetValue = 1; - } - else - { - RetValue = 0; - break; - } - } - Vk2c21_SCL_L(); - //单片机SDA脚为单向IO要设为输出脚 - Vk2c21_SET_SDA_OUT(); - //printk("---%s----ret=%d------\n",__func__,RetValue); - return RetValue; -} -/******************************************************************************* -* Function Name : I2CWriteByte -* Description : I2C写一字节命令,命令先送高位 -* Input : byte-要写入的数据 -* Output : None -* Return : None -*******************************************************************************/ -static void Vk2c21_I2CWriteByte( unsigned char byte ) -{ - unsigned char i=8; - while (i--) - { - Vk2c21_SCL_L(); - if(byte&0x80) - Vk2c21_SDA_H(); - else - Vk2c21_SDA_L(); - byte<<=1; - delay_nus(VK2c21_CLK); - Vk2c21_SCL_H(); - delay_nus(VK2c21_CLK); - } -} - -/************************************************************* -*函数名称: WriteCmdVk2c21 -*函数功能: 向Vk2C23写1个命令 -*输入参数: addr Dmod地址 - data 写入的数据 -*输出参数：SET: 写入正常；RESET:写入错误 -*备 注： -**************************************************************/ -static unsigned char WriteCmdVk2c21(unsigned char cmd, unsigned char data ) -{ - Vk2c21_I2CStart(); - - Vk2c21_I2CWriteByte( Vk2c21_ADDR|0x00 ); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - Vk2c21_I2CWriteByte( cmd ); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - Vk2c21_I2CWriteByte( data ); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - Vk2c21_I2CStop(); - - return 0; //返回操作成败标志 -} -/******************************************************************************* -* Function Name : Write1Data -* Description : 写1字节数据到显示RAM -* Input : Addr-写入ram的地址 -* : Dat->写入ram的数据 -* Output : None -* Return : 0-ok 1-fail -*******************************************************************************/ -static unsigned char Write1DataVk2c21(unsigned char Addr,unsigned char Dat) -{ - //START 信号 - Vk2c21_I2CStart(); - //SLAVE地址 - Vk2c21_I2CWriteByte(Vk2c21_ADDR); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 1; - } - //写显示RAM命令 - Vk2c21_I2CWriteByte(Vk2c21_RWRAM); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - //显示RAM地址 - Vk2c21_I2CWriteByte(Addr); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 1; - } - //显示数据，1字节数据包含2个SEG - Vk2c21_I2CWriteByte(Dat); - if( Vk2c21_I2CSlaveAck()==1 ) - { - Vk2c21_I2CStop(); - return 1; - } - //STOP信号 - Vk2c21_I2CStop(); - return 0; -} -/******************************************************************************* -* Function Name : WritenData -* Description : 写多个数据到显示RAM -* Input : Addr-写入ram的起始地址 -* : Databuf->写入ram的数据buffer指针 -* : Cnt->写入ram的数据个数 -* Output : None -* Return : 0-ok 1-fail -*******************************************************************************/ -static unsigned char WritenDataVk2c21(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt) -{ - unsigned char n; - - //START信号 - Vk2c21_I2CStart(); - //SLAVE地址 - Vk2c21_I2CWriteByte(Vk2c21_ADDR); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - //写显示RAM命令 - Vk2c21_I2CWriteByte(Vk2c21_RWRAM); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - //显示RAM起始地址 - Vk2c21_I2CWriteByte(Addr); - if( 1 == Vk2c21_I2CSlaveAck() ) - { - Vk2c21_I2CStop(); - return 0; - } - //发送Cnt个数据到显示RAM - for(n=0;n写入ram的数据(1个字节数据对应2个SEG) -* Output : None -* Return : None -*******************************************************************************/ -static void Vk2c21_DisAll(unsigned char dat) -{ - unsigned char segi; - unsigned char dispram[16]; - - if(vk2c21_maxcom==4) - { - for(segi=0;segi<10;segi++) - { - dispram[segi]=dat; - } - WritenDataVk2c21(0,dispram,10);//这里送8bit数据对应2个SEG，每8bit数据地址加1，每8位数据1个ACK - } - else - { - for(segi=0;segi<16;segi++) - { - dispram[segi]=dat; - } - WritenDataVk2c21(0,dispram,16);//这里送8bit数据对应1个SEG，每8bit数据地址加1，每8位数据1个ACK - } -} -/******************************************************************************* -* Function Name : DisSegComOn -* Description : 点亮1个点(1个seg和1个com交叉对应的显示点) -* Input ：seg->点对应的seg脚 -* ：com->点对应com脚 -* Output : None -* Return : None -*******************************************************************************/ -static void Vk2c21_DisSegComOn(unsigned char seg,unsigned char com) -{ - if(vk2c21_maxcom==4) - { - if(seg%2==0) - Write1DataVk2c21(seg/2,(1<<(com)));//这里送8位数据低4bit有效，每8bit数据地址加1，每8位数据1个ACK) - else - Write1DataVk2c21(seg/2,(1<<(4+com)));//这里送8位数据高4bit有效，每8bit数据地址加1，每8位数据1个ACK - } - else - { - Write1DataVk2c21(seg,(1<<(com)));//这里送8位数据低4bit有效，每8bit数据地址加1，每8位数据1个ACK - } -} -/******************************************************************************* -* Function Name : DisSegComOff -* Description : 关闭1个点(1个seg和1个com交叉对应的显示点) -* Input ：seg->点对应的seg脚 -* ：com->点对应com脚 -* Output : None -* Return : None -*******************************************************************************/ -static void Vk2c21_DisSegComOff(unsigned char seg,unsigned char com) -{ - if(vk2c21_maxcom==4) - { - if(seg%2==0) - Write1DataVk2c21(seg/2,~(1<0偏置电压=VLCD - WriteCmdVk2c21(Vk2c21_IVASET,VLCDSEL_IVAOFF_R1); - //SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.652VDD 1/4bias=0.714VDD - //WriteCmdVk2c21(Vk2c21_IVASET,SEGSEL_IVA02H); - - //test - Vk2c21_DisAll(0x00); - disp_3num(456); - //Vk2c21_DisAll(0xff); //LCD全显 - //disp_3num(1234); - return ret; -} - -static int Vk2c21_open(struct inode *inode, struct file *file) -{ - int ret; - ret = nonseekable_open(inode, file); - if(ret < 0) - return ret; - return 0; -} - -static int Vk2c21_release(struct inode *inode, struct file *file) -{ - return 0; -} - -static long Vk2c21_ioctl(struct file *file, unsigned int cmd, unsigned long args) -{ - int ret = 0 , i=0,pos_temp=0; - void __user *argp = (void __user *)args; - unsigned char display_arg[6]={0}; - switch (cmd){ - case IOCTL_CHAR_DISPLAY: - if (args) { - ret = copy_from_user(display_arg, argp,sizeof(display_arg)/sizeof(display_arg[0])); - } - for(i=0;i<6;i++) - { - if(display_arg[i] <= '9' && display_arg[i] >= '0') - { - pos_temp = display_arg[i] - '0'; - vk2c21_dispram[i]&=0xf0; - vk2c21_dispram[i]|=shuzi_zimo[pos_temp]&0x0f; - vk2c21_dispram[i]&=0x8f; - vk2c21_dispram[i]|=shuzi_zimo[pos_temp]&0xf0; - Write1DataVk2c21(vk2c21_segtab[2*i+2]/2,vk2c21_dispram[i]); - }else if(display_arg[i] <= 'z' && display_arg[i] >= 'a'){ - }else if(display_arg[i] <= 'Z' && display_arg[i] >= 'A'){ - } - } - break; - case IOCTL_DOT_DISPLAY: - break; - case IOCTL_COLON_DISPLAY: - break; - case IOCTL_PWR_DISPLAY: - break; - case IOCTL_LAN_DISPLAY: - Vk2c21_DisSegComOn(vk2c21_segtab[6],0x1); - break; - case IOCTL_LAN_OFF: - Vk2c21_DisSegComOff(vk2c21_segtab[6],0x1); - break; - case IOCTL_WIFI_LOW_DISPLAY: - break; - case IOCTL_WIFI_FINE_DISPLAY: - break; - case IOCTL_WIFI_OFF: - break; - case IOCTL_LED_ON: - Vk2c21_DisAll(0xff); //LCD全显 - break; - case IOCTL_LED_OFF: - Vk2c21_DisAll(0x00); //LCD全关 - break; - default: - printk("ERROR: IOCTL CMD NOT FOUND!!!\n"); - break; - } - return 0; -} -static struct file_operations Vk2c21_fops ={ - .owner =THIS_MODULE, - .open =Vk2c21_open, - .release =Vk2c21_release, - .unlocked_ioctl =Vk2c21_ioctl, -}; - - - -static int Vk2c21_probe(struct platform_device *pdev) -{ - static struct class * scull_class; - struct device_node *node = pdev->dev.of_node; - enum of_gpio_flags flags; - int ret; - - ret =register_chrdev(0,DEVICE_NAME,&Vk2c21_fops); - if(ret<0){ - printk("can't register device lcd_vk2c21.\n"); - return ret; - } - printk("register device lcd_vk2c21 success.\n"); - - scull_class = class_create(THIS_MODULE,DEVICE_NAME); - if(IS_ERR(scull_class)) - { - printk(KERN_ALERT "Err:faile in scull_class!\n"); - return -1; - } - device_create(scull_class, NULL, MKDEV(ret,0), NULL, DEVICE_NAME); - - - //--------------------------- - gpio_i2c_scl = of_get_named_gpio_flags(node, "i2c_scl", 0, &flags); - if (gpio_is_valid(gpio_i2c_scl)){ - if (gpio_request(gpio_i2c_scl, "i2c_scl_gpio")<0) { - printk("%s: failed to get gpio_i2c_scl.\n", __func__); - return -1; - } - gpio_direction_output(gpio_i2c_scl, 1); - printk("%s: get property: gpio,i2c_scl = %d\n", __func__, gpio_i2c_scl); - }else{ - printk("get property gpio,i2c vk2c21 failed \n"); - return -1; - } - - gpio_i2c_sda = of_get_named_gpio_flags(node, "i2c_sda", 0, &flags); - - if (gpio_is_valid(gpio_i2c_sda)){ - if (gpio_request(gpio_i2c_sda, "i2c_sda_gpio")<0) { - printk("%s: failed to get gpio_i2c_sda.\n", __func__); - return -1; - } - gpio_direction_output(gpio_i2c_sda, 1); - printk("%s: get property: gpio,i2c_sda = %d\n", __func__, gpio_i2c_sda); - }else{ - printk("get property gpio,i2c vk2c21 failed \n"); - return -1; - } - - printk("==========%s probe ok========\n", DEVICE_NAME); - - ret = Vk2c21_Init(); - if(ret < 0) - return -1; - - - return 0; -} - -static int Vk2c21_remove(struct platform_device *pdev) -{ - unregister_chrdev(0,DEVICE_NAME); - return 0; -} - - -static void Vk2c21_shutdown (struct platform_device *pdev) -{ - WriteCmdVk2c21(Vk2c21_SYSSET,SYSOFF_LCDOFF); -} - -#ifdef CONFIG_OF -static const struct of_device_id Vk2c21_dt_match[]={ - { .compatible = "lcd_vk2c21",}, - {} -}; -MODULE_DEVICE_TABLE(of, Vk2c21_dt_match); -#endif - -static struct platform_driver Vk2c21_driver = { - .probe = Vk2c21_probe, - .remove = Vk2c21_remove, - .shutdown = Vk2c21_shutdown, - .driver = { - .name = DEVICE_NAME, - .owner = THIS_MODULE, -#ifdef CONFIG_OF - .of_match_table = of_match_ptr(Vk2c21_dt_match), -#endif - }, -}; - - -static int __init led_vk2c21_init(void) -{ - int ret; - DBG_PRINT("%s\n=============================================\n", __FUNCTION__); - ret = platform_driver_register(&Vk2c21_driver); - if (ret) { - printk("[error] %s failed to register vk2c21 driver module\n", __FUNCTION__); - return -ENODEV; - } - return ret; -} - -static void __exit led_vk2c21_exit(void) -{ - platform_driver_unregister(&Vk2c21_driver); -} - -module_init(led_vk2c21_init); -module_exit(led_vk2c21_exit); - -MODULE_AUTHOR("Hugsun"); -MODULE_DESCRIPTION("LCD Extern driver for lcd_vk2c21"); -MODULE_LICENSE("GPL"); diff --git a/drivers/char/lcd_vk2c21.h b/drivers/char/lcd_vk2c21.h deleted file mode 100644 index ac6dd04442474..0000000000000 --- a/drivers/char/lcd_vk2c21.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __LCD_VK2C21_H__ -#define __LCD_VK2C21_H__ - -#define Vk2c21_ADDR 0x70 // IIC地址 -//基本设置 -#define Vk2c21_RWRAM 0x80 // 读写显示RAM -#define Vk2c21_MODESET 0x82 // BIAS,COM设置 -#define CCOM_1_3__4 0x00 // 1/3bias 4com -#define CCOM_1_4__4 0x01 // 1/4bias 4com -#define CCOM_1_3__8 0x02 // 1/3bias 8com -#define CCOM_1_4__8 0x03 // 1/4bias 8com -#define Vk2c21_SYSSET 0x84 // IRC,LCD开关设置 -#define SYSOFF_LCDOFF 0x00 // IRC off,LCD off -#define SYSON_LCDOFF 0x02 // IRC on,LCD off -#define SYSON_LCDON 0x03 // IRC on,LCD on -#define Vk2c21_FRAMESET 0x86 // 帧频设置 -#define FRAME_80HZ 0x00 // 帧频80HZ -#define FRAME_160HZ 0x01 // 帧频160HZ -#define Vk2c21_BLINKSET 0x88 // 闪烁频率设置 -#define BLINK_OFF 0x00 // 闪烁关闭 -#define BLINK_2HZ 0x01 // 闪烁2HZ -#define BLINK_1HZ 0x02 // 闪烁1HZ -#define BLINK_0D5HZ 0x03 // 闪烁0.5HZ -#define Vk2c21_IVASET 0x8A // SEG/VLCD共用脚设置和内部电压调整设置 -#define VLCDSEL_IVAOFF_R0 0x00 // SEG/VLCD共用脚设为VLCD，内部电压调整功能关闭,VLCD和VDD短接VR=0偏置电压=VDD -#define VLCDSEL_IVAOFF_R1 0x0F // SEG/VLCD共用脚设为VLCD，内部电压调整功能关闭,VLCD和VDD串接电阻VR>0偏置电压=VLCD - -#define VLCDSEL_IVA00H 0x10 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=VDD 1/4bias=VDD -#define VLCDSEL_IVA01H 0x11 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.944VDD 1/4bias=0.957VDD -#define VLCDSEL_IVA02H 0x12 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.894VDD 1/4bias=0.918VDD -#define VLCDSEL_IVA03H 0x13 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.849VDD 1/4bias=0.882VDD -#define VLCDSEL_IVA04H 0x14 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.808VDD 1/4bias=0.849VDD -#define VLCDSEL_IVA05H 0x15 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.771VDD 1/4bias=0.818VDD -#define VLCDSEL_IVA06H 0x16 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.738VDD 1/4bias=0.789VDD -#define VLCDSEL_IVA07H 0x17 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.707VDD 1/4bias=0.763VDD -#define VLCDSEL_IVA08H 0x18 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.678VDD 1/4bias=0.738VDD -#define VLCDSEL_IVA09H 0x19 // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.652VDD 1/4bias=0.714VDD -#define VLCDSEL_IVA0AH 0x1A // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.628VDD 1/4bias=0.692VDD -#define VLCDSEL_IVA0BH 0x1B // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.605VDD 1/4bias=0.672VDD -#define VLCDSEL_IVA0CH 0x1C // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.584VDD 1/4bias=0.652VDD -#define VLCDSEL_IVA0DH 0x1D // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.565VDD 1/4bias=0.634VDD -#define VLCDSEL_IVA0EH 0x1E // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.547VDD 1/4bias=0.616VDD -#define VLCDSEL_IVA0FH 0x1F // SEG/VLCD共用脚设为VLCD输出，内部偏置电压调整：1/3bias=0.529VDD 1/4bias=0.600VDD - -#define SEGSEL_IVAOFF 0x20 // SEG/VLCD共用脚设为SEG，内部电压调整功能关闭,VDD提供偏置电压 -#define SEGSEL_IVA00H 0x30 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=VDD 1/4bias=VDD -#define SEGSEL_IVA01H 0x31 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.944VDD 1/4bias=0.957VDD -#define SEGSEL_IVA02H 0x32 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.894VDD 1/4bias=0.918VDD -#define SEGSEL_IVA03H 0x33 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.849VDD 1/4bias=0.882VDD -#define SEGSEL_IVA04H 0x34 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.808VDD 1/4bias=0.849VDD -#define SEGSEL_IVA05H 0x35 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.771VDD 1/4bias=0.818VDD -#define SEGSEL_IVA06H 0x36 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.738VDD 1/4bias=0.789VDD -#define SEGSEL_IVA07H 0x37 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.707VDD 1/4bias=0.763VDD -#define SEGSEL_IVA08H 0x38 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.678VDD 1/4bias=0.738VDD -#define SEGSEL_IVA09H 0x39 // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.652VDD 1/4bias=0.714VDD -#define SEGSEL_IVA0AH 0x3A // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.628VDD 1/4bias=0.692VDD -#define SEGSEL_IVA0BH 0x3B // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.605VDD 1/4bias=0.672VDD -#define SEGSEL_IVA0CH 0x3C // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.584VDD 1/4bias=0.652VDD -#define SEGSEL_IVA0DH 0x3D // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.565VDD 1/4bias=0.634VDD -#define SEGSEL_IVA0EH 0x3E // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.547VDD 1/4bias=0.616VDD -#define SEGSEL_IVA0FH 0x3F // SEG/VLCD共用脚设为SEG，内部偏置电压调整：1/3bias=0.529VDD 1/4bias=0.600VDD - -#endif From 5019ef468a949409cb3033248b697f1f42f68386 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sat, 16 May 2026 09:49:13 +0200 Subject: [PATCH 03/32] auxdisplay: add a driver for Vinka VK2C21 Segment LCD Controller - Original from https://github.com/armbian/build/commit/5ee03afdb5d90556d3686b9cd03448cb0dde2193 - backported from 7.0.y mainline version to 6.1.y - `.remove` returns void at 6.1.y The Vinka VK2C21 (and pin-compatible VK2C21A/VK2C21B) is a memory-mapping segment LCD controller that communicates over I2C. It can drive up to 128 segments (e.g. 32 SEG x 4 COM in 1/3 bias mode). Some SBCs wire this chip to GPIO pins without I2C pull-up resistors, making the standard i2c-gpio (open-drain) driver unusable. This driver therefore bit-bangs I2C in push-pull mode directly via GPIO, requiring no external pull-ups. Signed-off-by: Ricardo Pardini --- .../bindings/auxdisplay/vinka,vk2c21.yaml | 59 ++ drivers/auxdisplay/Kconfig | 13 + drivers/auxdisplay/Makefile | 1 + drivers/auxdisplay/lcd-vk2c21.c | 519 ++++++++++++++++++ 4 files changed, 592 insertions(+) create mode 100644 Documentation/devicetree/bindings/auxdisplay/vinka,vk2c21.yaml create mode 100644 drivers/auxdisplay/lcd-vk2c21.c diff --git a/Documentation/devicetree/bindings/auxdisplay/vinka,vk2c21.yaml b/Documentation/devicetree/bindings/auxdisplay/vinka,vk2c21.yaml new file mode 100644 index 0000000000000..bdaeb1bd634d6 --- /dev/null +++ b/Documentation/devicetree/bindings/auxdisplay/vinka,vk2c21.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/auxdisplay/vinka,vk2c21.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Vinka VK2C21 Segment LCD Controller + +maintainers: + - Ricardo Pardini + +description: | + The Vinka VK2C21 (and pin-compatible VK2C21A/VK2C21B) is a memory-mapping + segment LCD controller that communicates over I2C. It can drive up to + 128 segments (e.g. 32 SEG × 4 COM in 1/3 bias mode). + + Many low-cost SBCs wire this chip to GPIO pins without I2C pull-up + resistors, making the standard i2c-gpio (open-drain) driver unusable. + This driver therefore bit-bangs I2C in push-pull mode directly via GPIO, + requiring no external pull-ups. + +properties: + compatible: + const: vinka,vk2c21 + + sda-gpios: + description: GPIO line used for I2C SDA (data). + maxItems: 1 + + scl-gpios: + description: GPIO line used for I2C SCL (clock). + maxItems: 1 + + clock-frequency: + description: Desired I2C clock frequency in Hz. + default: 100000 + minimum: 1000 + maximum: 400000 + +required: + - compatible + - sda-gpios + - scl-gpios + +additionalProperties: false + +examples: + - | + #include + #include + + / { + segment-lcd { + compatible = "vinka,vk2c21"; + sda-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + clock-frequency = <100000>; + }; + }; diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig index 64012cda4d126..89494c4ddbbd4 100644 --- a/drivers/auxdisplay/Kconfig +++ b/drivers/auxdisplay/Kconfig @@ -510,6 +510,19 @@ choice endchoice +config LCD_VK2C21 + tristate "Vinka VK2C21 segment LCD controller" + depends on GPIOLIB + depends on OF + help + Say Y or M here to add support for the Vinka VK2C21 segment LCD + controller found on various Rockchip-based SBCs (e.g. Mekotronics + R58X). The chip communicates via I2C but is often wired without + pull-up resistors, so this driver bit-bangs I2C in push-pull mode + directly via GPIO. + + The display text is controlled via sysfs. + endif # AUXDISPLAY config PANEL diff --git a/drivers/auxdisplay/Makefile b/drivers/auxdisplay/Makefile index 6968ed4d3f0a8..bcd478240f5d3 100644 --- a/drivers/auxdisplay/Makefile +++ b/drivers/auxdisplay/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_HT16K33) += ht16k33.o obj-$(CONFIG_PARPORT_PANEL) += panel.o obj-$(CONFIG_LCD2S) += lcd2s.o obj-$(CONFIG_LINEDISP) += line-display.o +obj-$(CONFIG_LCD_VK2C21) += lcd-vk2c21.o diff --git a/drivers/auxdisplay/lcd-vk2c21.c b/drivers/auxdisplay/lcd-vk2c21.c new file mode 100644 index 0000000000000..ee181bf57f7c3 --- /dev/null +++ b/drivers/auxdisplay/lcd-vk2c21.c @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for Vinka VK2C21 segment LCD controller + * + * The VK2C21 is accessed via I2C but many boards (especially Rockchip-based + * SBCs) wire it without pull-up resistors, so the standard i2c-gpio driver + * (open-drain) cannot communicate with it. This driver therefore bit-bangs + * I2C in push-pull mode directly via GPIO. + * + * Datasheet: https://www.lcsc.com/datasheet/lcsc_datasheet_2302080930_VINKA-VK2C21A_C5358619.pdf + * + * Copyright (C) 2025 Ricardo Pardini + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * VK2C21 I2C address. The chip has a single fixed address whose 8-bit + * write form is 0x70 (7-bit: 0x38). We bit-bang the 8-bit value directly. + */ +#define VK2C21_ADDR_W 0x70 + +/* VK2C21 command bytes (directly from the datasheet) */ +#define VK2C21_RWRAM 0x80 +#define VK2C21_MODESET 0x82 +#define VK2C21_SYSSET 0x84 +#define VK2C21_FRAMESET 0x86 +#define VK2C21_BLINKSET 0x88 +#define VK2C21_IVASET 0x8A + +/* Register values */ +#define VK2C21_BIAS_1_3_4COM 0x00 /* 1/3 bias, 4 COM */ +#define VK2C21_SYS_ON_LCD_ON 0x03 /* System + LCD on */ +#define VK2C21_SYS_OFF_LCD_OFF 0x00 /* System + LCD off */ +#define VK2C21_FRAME_80HZ 0x00 /* 80 Hz frame rate */ +#define VK2C21_BLINK_OFF 0x00 /* Blinking off */ +#define VK2C21_IVA_DEFAULT 0x0F /* VLCD selected, IVA off, R1 */ + +/* Display RAM has 10 addressable bytes (SEG/COM matrix) */ +#define VK2C21_RAM_SIZE 10 + +/* We support a 6-digit display */ +#define VK2C21_MAX_DIGITS 6 + +/* + * Segment encoding table. + * Maps digit positions (0..5, left to right) to VK2C21 RAM addresses. + * This table is board-specific; the values below match the common Mekotronics + * and similar Rockchip SBC wiring. + */ +static const u8 vk2c21_digit_to_ram[] = { 8, 7, 6, 5, 4, 3 }; + +/* + * 7-segment bit mapping for this hardware: + * + * ─── a ─── + * │ │ bit 7 = a (top) + * f b bit 6 = f (upper-left) + * │ │ bit 5 = e (lower-left) + * ─── g ─── bit 4 = d (bottom) + * │ │ bit 2 = b (upper-right) + * e c bit 1 = g (middle) + * │ │ bit 0 = c (lower-right) + * ─── d ─── bit 3 = unused (DP on some boards) + */ +#define SEG_A 0x80 +#define SEG_B 0x04 +#define SEG_C 0x01 +#define SEG_D 0x10 +#define SEG_E 0x20 +#define SEG_F 0x40 +#define SEG_G 0x02 + +#define VK2C21_FONT_BLANK 0x00 + +/* + * Full 7-segment ASCII font table. + * 0x00 = character cannot be meaningfully represented → blank. + * Lowercase letters use the conventional 7-segment representations. + * + * Characters that are indistinguishable from digits or other letters + * on a 7-segment display (e.g. 'S' vs '5', 'Z' vs '2') are still + * included so that arbitrary text can be displayed. + */ +static const u8 vk2c21_ascii_font[128] = { + /* 0x20 ' ' */ [' '] = VK2C21_FONT_BLANK, + /* 0x21 '!' */ ['!'] = SEG_B | SEG_C, /* same as 1 */ + /* 0x22 '"' */ ['"'] = SEG_B | SEG_F, + /* 0x27 ''' */ ['\''] = SEG_F, + /* 0x28 '(' */ ['('] = SEG_A | SEG_D | SEG_E | SEG_F, /* same as [ */ + /* 0x29 ')' */ [')'] = SEG_A | SEG_B | SEG_C | SEG_D, /* same as ] */ + /* 0x2c ',' */ [','] = SEG_C, + /* 0x2d '-' */ ['-'] = SEG_G, + /* 0x2f '/' */ ['/'] = SEG_B | SEG_E | SEG_G, + /* 0x30-0x39: digits */ + ['0'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, + ['1'] = SEG_B | SEG_C, + ['2'] = SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, + ['3'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, + ['4'] = SEG_B | SEG_C | SEG_F | SEG_G, + ['5'] = SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, + ['6'] = SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, + ['7'] = SEG_A | SEG_B | SEG_C, + ['8'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, + ['9'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, + /* 0x3d '=' */ ['='] = SEG_D | SEG_G, + /* 0x3f '?' */ ['?'] = SEG_A | SEG_B | SEG_E | SEG_G, + /* Uppercase letters */ + ['A'] = SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, + ['B'] = SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* same as b */ + ['C'] = SEG_A | SEG_D | SEG_E | SEG_F, + ['D'] = SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* same as d */ + ['E'] = SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, + ['F'] = SEG_A | SEG_E | SEG_F | SEG_G, + ['G'] = SEG_A | SEG_C | SEG_D | SEG_E | SEG_F, + ['H'] = SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, + ['I'] = SEG_E | SEG_F, + ['J'] = SEG_B | SEG_C | SEG_D | SEG_E, + /* K: not cleanly representable, approximate as H */ + ['K'] = SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, + ['L'] = SEG_D | SEG_E | SEG_F, + /* M: not representable on 7-seg, skip (will show blank) */ + ['N'] = SEG_C | SEG_E | SEG_G, /* same as n */ + ['O'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* same as 0 */ + ['P'] = SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, + ['Q'] = SEG_A | SEG_B | SEG_C | SEG_F | SEG_G, + ['R'] = SEG_E | SEG_G, /* same as r */ + ['S'] = SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* same as 5 */ + ['T'] = SEG_D | SEG_E | SEG_F | SEG_G, /* same as t */ + ['U'] = SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, + ['V'] = SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* same as U */ + /* W: not representable on 7-seg, skip */ + /* X: not cleanly representable, approximate as H */ + ['X'] = SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, + ['Y'] = SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, + ['Z'] = SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* same as 2 */ + ['['] = SEG_A | SEG_D | SEG_E | SEG_F, + [']'] = SEG_A | SEG_B | SEG_C | SEG_D, + ['_'] = SEG_D, + /* Lowercase letters */ + ['a'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, + ['b'] = SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, + ['c'] = SEG_D | SEG_E | SEG_G, + ['d'] = SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, + ['e'] = SEG_A | SEG_B | SEG_D | SEG_E | SEG_F | SEG_G, + ['f'] = SEG_A | SEG_E | SEG_F | SEG_G, /* same as F */ + ['g'] = SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* same as 9 */ + ['h'] = SEG_C | SEG_E | SEG_F | SEG_G, + ['i'] = SEG_C, + ['j'] = SEG_B | SEG_C | SEG_D, + /* k: approximate as h */ + ['k'] = SEG_C | SEG_E | SEG_F | SEG_G, + ['l'] = SEG_E | SEG_F, + /* m: not representable on 7-seg, skip */ + ['n'] = SEG_C | SEG_E | SEG_G, + ['o'] = SEG_C | SEG_D | SEG_E | SEG_G, + ['p'] = SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* same as P */ + ['q'] = SEG_A | SEG_B | SEG_C | SEG_F | SEG_G, /* same as Q */ + ['r'] = SEG_E | SEG_G, + ['s'] = SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* same as 5 */ + ['t'] = SEG_D | SEG_E | SEG_F | SEG_G, + ['u'] = SEG_C | SEG_D | SEG_E, + ['v'] = SEG_C | SEG_D | SEG_E, /* same as u */ + /* w: not representable */ + /* x: approximate as H */ + ['x'] = SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, + ['y'] = SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* same as Y */ + ['z'] = SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* same as 2 */ + /* 0x7c '|' */ ['|'] = SEG_E | SEG_F, + /* 0x7e '~' */ ['~'] = SEG_A, +}; + +struct vk2c21_data { + struct device *dev; + struct gpio_desc *sda; + struct gpio_desc *scl; + struct mutex lock; /* serialises I2C access */ + unsigned int half_period_ns; + u8 dispram[VK2C21_RAM_SIZE]; + char display_text[VK2C21_MAX_DIGITS + 1]; +}; + +/* ------------------------------------------------------------------ */ +/* Low-level push-pull bit-bang I2C */ +/* ------------------------------------------------------------------ */ + +static inline void sda_high(struct vk2c21_data *d) +{ + gpiod_direction_output(d->sda, 1); +} + +static inline void sda_low(struct vk2c21_data *d) +{ + gpiod_direction_output(d->sda, 0); +} + +static inline void scl_high(struct vk2c21_data *d) +{ + gpiod_set_value(d->scl, 1); +} + +static inline void scl_low(struct vk2c21_data *d) +{ + gpiod_set_value(d->scl, 0); +} + +static inline int sda_read(struct vk2c21_data *d) +{ + gpiod_direction_input(d->sda); + return gpiod_get_value(d->sda); +} + +static inline void bb_delay(struct vk2c21_data *d) +{ + ndelay(d->half_period_ns); +} + +static void bb_start(struct vk2c21_data *d) +{ + scl_high(d); + sda_high(d); + bb_delay(d); + sda_low(d); + bb_delay(d); +} + +static void bb_stop(struct vk2c21_data *d) +{ + scl_high(d); + sda_low(d); + bb_delay(d); + sda_high(d); + bb_delay(d); +} + +/* Write one byte MSB-first; returns 0 on ACK, 1 on NACK */ +static int bb_write_byte(struct vk2c21_data *d, u8 byte) +{ + int i, ack; + + for (i = 7; i >= 0; i--) { + scl_low(d); + if (byte & BIT(i)) + sda_high(d); + else + sda_low(d); + bb_delay(d); + scl_high(d); + bb_delay(d); + } + + /* Clock the ACK/NACK bit */ + scl_low(d); + ack = sda_read(d); + bb_delay(d); + scl_high(d); + bb_delay(d); + scl_low(d); + sda_high(d); + + return ack; +} + +/* Send a two-byte command: [ADDR_W] [cmd] [data] */ +static int vk2c21_send_cmd(struct vk2c21_data *d, u8 cmd, u8 data) +{ + int ret = 0; + + bb_start(d); + if (bb_write_byte(d, VK2C21_ADDR_W)) { ret = -EIO; goto out; } + if (bb_write_byte(d, cmd)) { ret = -EIO; goto out; } + if (bb_write_byte(d, data)) { ret = -EIO; goto out; } +out: + bb_stop(d); + if (ret) + dev_err(d->dev, "command 0x%02x 0x%02x failed (no ACK)\n", + cmd, data); + return ret; +} + +/* Write one byte to display RAM: [ADDR_W] [0x80] [addr] [data] */ +static int vk2c21_write_ram(struct vk2c21_data *d, u8 addr, u8 data) +{ + int ret = 0; + + bb_start(d); + if (bb_write_byte(d, VK2C21_ADDR_W)) { ret = -EIO; goto out; } + if (bb_write_byte(d, VK2C21_RWRAM)) { ret = -EIO; goto out; } + if (bb_write_byte(d, addr)) { ret = -EIO; goto out; } + if (bb_write_byte(d, data)) { ret = -EIO; goto out; } +out: + bb_stop(d); + if (ret) + dev_err(d->dev, "write RAM[%u]=0x%02x failed\n", addr, data); + return ret; +} + +/* ------------------------------------------------------------------ */ +/* Display helpers */ +/* ------------------------------------------------------------------ */ + +static int vk2c21_clear(struct vk2c21_data *d) +{ + int i, ret; + + memset(d->dispram, 0, sizeof(d->dispram)); + for (i = 0; i < VK2C21_RAM_SIZE; i++) { + ret = vk2c21_write_ram(d, i, 0x00); + if (ret) + return ret; + } + return 0; +} + +static int vk2c21_init_hw(struct vk2c21_data *d) +{ + int ret; + + ret = vk2c21_send_cmd(d, VK2C21_MODESET, VK2C21_BIAS_1_3_4COM); + if (ret) return ret; + ret = vk2c21_send_cmd(d, VK2C21_SYSSET, VK2C21_SYS_ON_LCD_ON); + if (ret) return ret; + ret = vk2c21_send_cmd(d, VK2C21_FRAMESET, VK2C21_FRAME_80HZ); + if (ret) return ret; + ret = vk2c21_send_cmd(d, VK2C21_BLINKSET, VK2C21_BLINK_OFF); + if (ret) return ret; + ret = vk2c21_send_cmd(d, VK2C21_IVASET, VK2C21_IVA_DEFAULT); + if (ret) return ret; + + return vk2c21_clear(d); +} + +static u8 vk2c21_char_to_glyph(char c) +{ + if (c >= 0 && c < 128) + return vk2c21_ascii_font[(unsigned char)c]; + return VK2C21_FONT_BLANK; +} + +static int vk2c21_display_string(struct vk2c21_data *d, const char *str) +{ + int i, ret, len; + + len = strlen(str); + for (i = 0; i < VK2C21_MAX_DIGITS; i++) { + char c = (i < len) ? str[i] : ' '; + u8 glyph = vk2c21_char_to_glyph(c); + + ret = vk2c21_write_ram(d, vk2c21_digit_to_ram[i], glyph); + if (ret) + return ret; + } + return 0; +} + +/* ------------------------------------------------------------------ */ +/* sysfs interface */ +/* ------------------------------------------------------------------ */ + +static ssize_t display_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct vk2c21_data *d = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%s\n", d->display_text); +} + +static ssize_t display_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct vk2c21_data *d = dev_get_drvdata(dev); + char text[VK2C21_MAX_DIGITS + 1] = {}; + int ret, len; + + len = min_t(int, count, VK2C21_MAX_DIGITS); + if (len > 0 && buf[len - 1] == '\n') + len--; + memcpy(text, buf, len); + + mutex_lock(&d->lock); + ret = vk2c21_display_string(d, text); + if (!ret) { + memcpy(d->display_text, text, len); + d->display_text[len] = '\0'; + } + mutex_unlock(&d->lock); + + return ret ? ret : count; +} +static DEVICE_ATTR_RW(display); + +static ssize_t clear_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct vk2c21_data *d = dev_get_drvdata(dev); + int ret; + + mutex_lock(&d->lock); + ret = vk2c21_clear(d); + if (!ret) + d->display_text[0] = '\0'; + mutex_unlock(&d->lock); + + return ret ? ret : count; +} +static DEVICE_ATTR_WO(clear); + +static struct attribute *vk2c21_sysfs_attrs[] = { + &dev_attr_display.attr, + &dev_attr_clear.attr, + NULL, +}; + +static const struct attribute_group vk2c21_sysfs_group = { + .attrs = vk2c21_sysfs_attrs, +}; + +static const struct attribute_group *vk2c21_sysfs_groups[] = { + &vk2c21_sysfs_group, + NULL, +}; + +/* ------------------------------------------------------------------ */ +/* Platform driver */ +/* ------------------------------------------------------------------ */ + +static int vk2c21_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct vk2c21_data *d; + u32 freq = 100000; + int ret; + + d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); + if (!d) + return -ENOMEM; + + d->dev = dev; + mutex_init(&d->lock); + platform_set_drvdata(pdev, d); + + d->sda = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH); + if (IS_ERR(d->sda)) + return dev_err_probe(dev, PTR_ERR(d->sda), + "failed to get SDA GPIO\n"); + + d->scl = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH); + if (IS_ERR(d->scl)) + return dev_err_probe(dev, PTR_ERR(d->scl), + "failed to get SCL GPIO\n"); + + of_property_read_u32(dev->of_node, "clock-frequency", &freq); + if (!freq) + freq = 100000; + d->half_period_ns = 500000000U / freq; + + dev_info(dev, "I2C bitbang @ ~%u Hz, half-period %u ns\n", + freq, d->half_period_ns); + + mutex_lock(&d->lock); + ret = vk2c21_init_hw(d); + mutex_unlock(&d->lock); + if (ret) + return dev_err_probe(dev, ret, "hardware init failed\n"); + + dev_info(dev, "VK2C21 segment LCD ready\n"); + return 0; +} + +static int vk2c21_remove(struct platform_device *pdev) +{ + struct vk2c21_data *d = platform_get_drvdata(pdev); + + mutex_lock(&d->lock); + vk2c21_send_cmd(d, VK2C21_SYSSET, VK2C21_SYS_OFF_LCD_OFF); + mutex_unlock(&d->lock); + + return 0; +} + +static void vk2c21_shutdown(struct platform_device *pdev) +{ + struct vk2c21_data *d = platform_get_drvdata(pdev); + + mutex_lock(&d->lock); + vk2c21_send_cmd(d, VK2C21_SYSSET, VK2C21_SYS_OFF_LCD_OFF); + mutex_unlock(&d->lock); +} + +static const struct of_device_id vk2c21_of_match[] = { + { .compatible = "vinka,vk2c21" }, + { } +}; +MODULE_DEVICE_TABLE(of, vk2c21_of_match); + +static struct platform_driver vk2c21_driver = { + .probe = vk2c21_probe, + .remove = vk2c21_remove, + .shutdown = vk2c21_shutdown, + .driver = { + .name = "lcd-vk2c21", + .of_match_table = vk2c21_of_match, + .dev_groups = vk2c21_sysfs_groups, + }, +}; +module_platform_driver(vk2c21_driver); + +MODULE_AUTHOR("Ricardo Pardini "); +MODULE_DESCRIPTION("Vinka VK2C21 segment LCD controller driver (push-pull bitbang I2C)"); +MODULE_LICENSE("GPL"); From 5bb9830526d70af31eadb93bafefbab36dbd187d Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sat, 16 May 2026 09:58:29 +0200 Subject: [PATCH 04/32] arm64: dts: mekos: drop lcd_vk2c21 reference from boards that don't have it - also eat trailing whitespace --- .../rockchip/rk3588-blueberry-edge-v10.dtsi | 26 +++----- .../rockchip/rk3588-blueberry-edge-v12.dtsi | 24 +++----- .../rockchip/rk3588-blueberry-edge-v14.dtsi | 32 ++++------ .../rockchip/rk3588-blueberry-r58-hd3.dtsi | 61 ++++++++----------- 4 files changed, 56 insertions(+), 87 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi index ff28e52af7687..cbd7ef64761f8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v10.dtsi @@ -41,7 +41,7 @@ }; }; }; - + hdmiin-sound { compatible = "rockchip,hdmi"; rockchip,mclk-fs = <128>; @@ -52,7 +52,7 @@ rockchip,cpu = <&i2s7_8ch>; rockchip,codec = <&hdmirx_ctrler 0>; rockchip,jack-det; - }; + }; leds: leds { compatible = "gpio-leds"; @@ -88,14 +88,6 @@ linux,code = ; wakeup-source; }; - }; - - vk2c21_lcd { - compatible = "lcd_vk2c21"; - i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - - status = "disabled"; }; pcie30_avdd0v75: pcie30-avdd0v75 { @@ -134,7 +126,7 @@ regulator-max-microvolt = <3300000>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie30_en>; + pinctrl-0 = <&vcc3v3_pcie30_en>; gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 startup-delay-us = <10000>; vin-supply = <&vcc12v_dcin>; @@ -578,7 +570,7 @@ }; }; -&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <750000>; @@ -668,12 +660,12 @@ wifi_host_wake_irq: wifi-host-wake-irq { rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; }; - + wifi_poweren_gpio: wifi-poweren-gpio { rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; + }; }; - + buttons { pwrbtn: pwrbtn { rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -707,8 +699,8 @@ pcie { vcc3v3_pcie30_en: vcc3v3-pcie30-en { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - + }; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi index 3da66e7dded0e..33cefbe1eefeb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12.dtsi @@ -70,7 +70,7 @@ rockchip,cpu = <&i2s7_8ch>; rockchip,codec = <&hdmirx_ctrler 0>; rockchip,jack-det; - }; + }; leds: leds { compatible = "gpio-leds"; @@ -107,14 +107,6 @@ linux,code = ; wakeup-source; }; - }; - - vk2c21_lcd { - compatible = "lcd_vk2c21"; - i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - - status = "disabled";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; }; pcie30_avdd0v75: pcie30-avdd0v75 { @@ -153,7 +145,7 @@ regulator-max-microvolt = <3300000>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie30_en>; + pinctrl-0 = <&vcc3v3_pcie30_en>; gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 startup-delay-us = <10000>; vin-supply = <&vcc12v_dcin>; @@ -598,7 +590,7 @@ }; }; -&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <750000>; @@ -702,12 +694,12 @@ wifi_host_wake_irq: wifi-host-wake-irq { rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; }; - + wifi_poweren_gpio: wifi-poweren-gpio { rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; + }; }; - + buttons { pwrbtn: pwrbtn { rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -753,8 +745,8 @@ pcie { vcc3v3_pcie30_en: vcc3v3-pcie30-en { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - + }; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi index 862376cd61f47..4640792b508af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v14.dtsi @@ -71,7 +71,7 @@ rockchip,codec = <&hdmirx_ctrler 0>; rockchip,jack-det; }; - + leds: leds { compatible = "gpio-leds"; @@ -108,14 +108,6 @@ linux,code = ; wakeup-source; }; - }; - - vk2c21_lcd { - compatible = "lcd_vk2c21"; - i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - - status = "disabled";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; }; pcie30_avdd0v75: pcie30-avdd0v75 { @@ -154,7 +146,7 @@ regulator-max-microvolt = <3300000>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie30_en>; + pinctrl-0 = <&vcc3v3_pcie30_en>; gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 startup-delay-us = <10000>; vin-supply = <&vcc12v_dcin>; @@ -212,13 +204,13 @@ power-on_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; //GPIO_C4 }; - + ext_cam_clk: external-camera-clock { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "CLK_CAMERA_24MHZ"; #clock-cells = <0>; - }; + }; wireless_bluetooth: wireless-bluetooth { compatible = "bluetooth-platdata"; @@ -753,7 +745,7 @@ }; }; -&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <750000>; @@ -857,12 +849,12 @@ wifi_host_wake_irq: wifi-host-wake-irq { rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; }; - + wifi_poweren_gpio: wifi-poweren-gpio { rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; + }; }; - + buttons { pwrbtn: pwrbtn { rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -904,20 +896,20 @@ rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - + hdmiin { lt6911uxc_pin: lt6911uxc-pin { rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; - }; + }; pcie { vcc3v3_pcie30_en: vcc3v3-pcie30-en { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - + }; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-r58-hd3.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-r58-hd3.dtsi index 518eadc6d8890..240cfddd454c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-r58-hd3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-r58-hd3.dtsi @@ -36,7 +36,7 @@ rockchip,codec = <&hdmirx_ctrler 0>; rockchip,jack-det; }; - + es8388_sound: es8388-sound { status = "okay"; compatible = "rockchip,multicodecs-card"; @@ -66,8 +66,8 @@ lt6911_dc: lt6911-dc { compatible = "rockchip,dummy-codec"; #sound-dai-cells = <0>; - }; - + }; + lt6911_sound:lt6911-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -81,9 +81,9 @@ dailink1_master: simple-audio-card,codec { sound-dai = <<6911_dc>; }; - }; - - + }; + + leds: leds { compatible = "gpio-leds"; @@ -113,13 +113,6 @@ linux,code = ; wakeup-source; }; - }; - - vk2c21_lcd { - compatible = "lcd_vk2c21"; - i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - status = "disabled";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; }; pcie30_avdd0v75: pcie30-avdd0v75 { @@ -158,7 +151,7 @@ regulator-max-microvolt = <3300000>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie30_en>; + pinctrl-0 = <&vcc3v3_pcie30_en>; gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; //hugsun gpio1_c4 startup-delay-us = <10000>; vin-supply = <&vcc12v_dcin>; @@ -245,13 +238,13 @@ pinctrl-names = "default"; pinctrl-0 = <&modem_pwr>; }; - + ext_cam_clk: external-camera-clock { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "CLK_CAMERA_24MHZ"; #clock-cells = <0>; - }; + }; wireless_bluetooth: wireless-bluetooth { compatible = "bluetooth-platdata"; @@ -287,11 +280,11 @@ hpd-trigger-level = <1>; hdmirx-det-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&hdmim2_rx_cec - &hdmim2_rx_hpdin - &hdmim2_rx_sda - &hdmim2_rx_scl - &hdmirx_det>; + pinctrl-0 = <&hdmim2_rx_cec + &hdmim2_rx_hpdin + &hdmim2_rx_sda + &hdmim2_rx_scl + &hdmirx_det>; }; //hdmirx sound @@ -600,7 +593,7 @@ status = "okay"; }; -//RTL8111HS +//RTL8111HS &pcie2x1l1 { reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -646,7 +639,7 @@ }; }; -&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up +&vdd_log_s0 { //fox.luo@2022.05.26 don't wake up regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <750000>; @@ -745,12 +738,12 @@ wifi_host_wake_irq: wifi-host-wake-irq { rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; }; - + wifi_poweren_gpio: wifi-poweren-gpio { rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; + }; }; - + buttons { pwrbtn: pwrbtn { rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -786,7 +779,7 @@ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - + hdmiin { lt6911uxc_pin: lt6911uxc-pin { rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, @@ -797,22 +790,22 @@ hdmirx_det: hdmirx-det { rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; }; - }; + }; pcie { vcc3v3_pcie30_en: vcc3v3-pcie30-en { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - + }; + }; - sdmmc-pwr { + sdmmc-pwr { sdmmc_pwr: sdmmc-pwr { rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - modem { + modem { modem_pwr: modem-pwr { rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -824,7 +817,7 @@ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - + hdmi_enable_gpio { hdmi_enable_gpio: hdmi_enable_gpio{ rockchip,pins = @@ -935,7 +928,7 @@ &usbdrd_dwc3_0 { dr_mode = "otg"; - extcon = <&u2phy0>; + extcon = <&u2phy0>; status = "okay"; }; From 5cd0e481376b46963045fad8ef84f43dc26197c9 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sat, 16 May 2026 09:59:13 +0200 Subject: [PATCH 05/32] arm64: dts: meko-r58x-pro: switch lcd_vk2c21 to new vinka,vk2c21 - backported driver which works - also eat trailing whitespace --- ...k3588-blueberry-edge-v12-maizhuo-linux.dts | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts index c50ad4456d346..928bd958b7e72 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-blueberry-edge-v12-maizhuo-linux.dts @@ -10,28 +10,28 @@ #include "rk3588-linux.dtsi" / { - model = "RK3588 EDGE LP4x V1.2 MeiZhuo BlueBerry Board"; + model = "Mekotronics R58X-Pro"; // RK3588 EDGE LP4x V1.2 MeiZhuo BlueBerry Board compatible = "rockchip,rk3588-blueberry-edge-v12-linux", "rockchip,rk3588"; /delete-node/ chosen; - - vk2c21_lcd { - compatible = "lcd_vk2c21"; - i2c_scl = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - i2c_sda = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - - status = "okay";//"okay"; //zxLog_2022.9.20 for maozhuo time-lcd show; - }; + + lcd_vk2c21 { + compatible = "vinka,vk2c21"; + sda-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + clock-frequency = <100000>; + status = "okay"; + }; }; -&gpio_keys{ +&gpio_keys{ vol_up { debounce-interval = <0>; autorepeat = <1>; gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; label = "GPIO Key Vol+"; linux,code = ; - wakeup-source; - }; + wakeup-source; + }; vol_down { debounce-interval = <0>; @@ -40,5 +40,5 @@ label = "GPIO Key Vol-"; linux,code = ; wakeup-source; - }; + }; }; \ No newline at end of file From f6eb0cbbaafcc8f6537bcf8309fff55d2b3c2d14 Mon Sep 17 00:00:00 2001 From: Austin Lane Date: Mon, 6 Apr 2026 13:52:38 -0400 Subject: [PATCH 06/32] luckfox-lyra-zero-w: Default to onboard wifi antenna, add overlay for ipex. Currently the luckfox-lyra-zero-w defaults to using the ipex connector for wifi (not the onboard antenna). This has lead to user confusion. Use a gpio hog to set the antenna selection pin HIGH at boot, selecting the onboard by default. Add an overlay for switching to the ipex connector. --- arch/arm/boot/dts/overlay/Makefile | 1 + .../boot/dts/overlay/README.rockchip-overlays | 4 ++++ ...kchip-luckfox-lyra-zero-w-ipex-antenna.dts | 23 +++++++++++++++++++ .../dts/rk3506b-luckfox-lyra-zero-w-sd.dts | 15 ++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 arch/arm/boot/dts/overlay/rockchip-luckfox-lyra-zero-w-ipex-antenna.dts diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile index 792845071b05c..8308fac2c8443 100644 --- a/arch/arm/boot/dts/overlay/Makefile +++ b/arch/arm/boot/dts/overlay/Makefile @@ -8,6 +8,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ rockchip-luckfox-lyra-plus-spi0-1cs-spidev.dtbo \ rockchip-luckfox-lyra-plus-spi0-2cs-spidev.dtbo \ rockchip-luckfox-lyra-ultra-w-spi0-1cs-spidev.dtbo \ + rockchip-luckfox-lyra-zero-w-ipex-antenna.dtbo \ rockchip-luckfox-lyra-zero-w-spi0-1cs-spidev.dtbo \ rockchip-luckfox-lyra-zero-w-spi0-2cs-spidev.dtbo \ rockchip-luckfox-lyra-zero-w-spi1-1cs-spidev.dtbo \ diff --git a/arch/arm/boot/dts/overlay/README.rockchip-overlays b/arch/arm/boot/dts/overlay/README.rockchip-overlays index 67ebcdd491474..024ae9474e61f 100644 --- a/arch/arm/boot/dts/overlay/README.rockchip-overlays +++ b/arch/arm/boot/dts/overlay/README.rockchip-overlays @@ -28,6 +28,7 @@ for Luckfox Lyra Ultra W: - spi0-1cs-spidev for Luckfox Lyra Zero W: +- ipex-antenna - spi0-1cs-spidev - spi0-2cs-spidev - spi1-1cs-spidev @@ -73,6 +74,9 @@ Retains pin-compatibility with Luckfox Pico Plus. Enables SPI0 spidev on luckfox-lyra-ultra-w with one chipselect. Retains pin-compatibility with Luckfox Pico Ultra. +### luckfox-lyra-zero-w-ipex-antenna +Switches wifi/bluetooth from the onboard antenna to the external IPEX connector. + ### luckfox-lyra-zero-w-spi0-1cs-spidev Enables SPI0 spidev on luckfox-lyra-zero-w with one chipselect. Compatible with Raspberry Pi 'spi0-1cs' hats. diff --git a/arch/arm/boot/dts/overlay/rockchip-luckfox-lyra-zero-w-ipex-antenna.dts b/arch/arm/boot/dts/overlay/rockchip-luckfox-lyra-zero-w-ipex-antenna.dts new file mode 100644 index 0000000000000..34b05c1debb42 --- /dev/null +++ b/arch/arm/boot/dts/overlay/rockchip-luckfox-lyra-zero-w-ipex-antenna.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Switch wifi/bluetooth antenna from onboard to external IPEX connector + * on Luckfox Lyra Zero W. + */ + +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable IPEX antenna on luckfox-lyra-zero-w"; + compatible = "rockchip,rk3506b-lyra-zero"; + category = "misc"; + description = "Switch wifi/bluetooth from onboard antenna to external IPEX connector (GPIO1_C7 low)."; + }; +}; + +&gpio1 { + ant-sel-hog { + output-low; + }; +}; diff --git a/arch/arm/boot/dts/rk3506b-luckfox-lyra-zero-w-sd.dts b/arch/arm/boot/dts/rk3506b-luckfox-lyra-zero-w-sd.dts index d49be9146d4bf..719b4b2cc34ad 100644 --- a/arch/arm/boot/dts/rk3506b-luckfox-lyra-zero-w-sd.dts +++ b/arch/arm/boot/dts/rk3506b-luckfox-lyra-zero-w-sd.dts @@ -99,6 +99,21 @@ status = "okay"; }; +/**********gpio**********/ +&gpio1 { + /* + * Antenna selection GPIO + * output-high = Onboard antenna selected + * output-low = External (ipex) antenna selected + */ + ant-sel-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "ant-sel"; + }; +}; + /**********pinctrl**********/ &pinctrl { lcd { From 9bd271d7fa4aab0cffd2ac6f1fd8e26c857c46c2 Mon Sep 17 00:00:00 2001 From: Austin Lane Date: Sun, 5 Apr 2026 15:59:05 -0400 Subject: [PATCH 07/32] ebyte-ecb41-pge: Add spidev overlays (RPi-compatible) Adds spidev overlays for `ebyte-ecb41-pge` compatible with raspberry pi 40pin layout. Also increases CMA for Ebyte-ECB41-PGE from 4MB to 8MB to correct current CMA allocation errors when enabling these overlays + ethernet at the same time. --- arch/arm/boot/dts/overlay/Makefile | 3 ++ .../boot/dts/overlay/README.rockchip-overlays | 17 ++++++++ ...ckchip-ebyte-ecb41-pge-spi0-1cs-spidev.dts | 34 +++++++++++++++ ...ckchip-ebyte-ecb41-pge-spi0-2cs-spidev.dts | 41 +++++++++++++++++++ ...ckchip-ebyte-ecb41-pge-spi1-1cs-spidev.dts | 34 +++++++++++++++ arch/arm/boot/dts/rk3506g-ebyte-ecb41-pge.dts | 2 +- 6 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-1cs-spidev.dts create mode 100644 arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-2cs-spidev.dts create mode 100644 arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi1-1cs-spidev.dts diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile index 8308fac2c8443..e19b858232507 100644 --- a/arch/arm/boot/dts/overlay/Makefile +++ b/arch/arm/boot/dts/overlay/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + rockchip-ebyte-ecb41-pge-spi0-1cs-spidev.dtbo \ + rockchip-ebyte-ecb41-pge-spi0-2cs-spidev.dtbo \ + rockchip-ebyte-ecb41-pge-spi1-1cs-spidev.dtbo \ rockchip-forlinx-ok3506-s12-spi0-1cs-spidev.dtbo \ rockchip-forlinx-ok3506-s12-spi0-2cs-spidev.dtbo \ rockchip-forlinx-ok3506-s12-spi1-1cs-spidev.dtbo \ diff --git a/arch/arm/boot/dts/overlay/README.rockchip-overlays b/arch/arm/boot/dts/overlay/README.rockchip-overlays index 024ae9474e61f..bc51236679511 100644 --- a/arch/arm/boot/dts/overlay/README.rockchip-overlays +++ b/arch/arm/boot/dts/overlay/README.rockchip-overlays @@ -13,6 +13,11 @@ for RK3506: - disable-ethernet0 - disable-ethernet1 +for Ebyte ECB41-PGE: +- spi0-1cs-spidev +- spi0-2cs-spidev +- spi1-1cs-spidev + for Forlinx OK3506-S12: - spi0-1cs-spidev - spi0-2cs-spidev @@ -42,6 +47,18 @@ Disables `end0` ethernet adapter (`gmac0`, `mdio0`) to save power. ### rk3506-disable-ethernet1 Disables `end1` ethernet adapter (`gmac1`, `mdio1`) to save power. +### ebyte-ecb41-pge-spi0-1cs-spidev +Enables SPI0 spidev on ebyte-ecb41-pge with one chipselect. +Compatible with Raspberry Pi 'spi0-1cs' hats. + +### ebyte-ecb41-pge-spi0-2cs-spidev +Enables SPI0 spidev on ebyte-ecb41-pge with two chipselects. +Compatible with Raspberry Pi 'spi0-2cs' hats. + +### ebyte-ecb41-pge-spi1-1cs-spidev +Enables SPI1 spidev on ebyte-ecb41-pge with one chipselect. +Compatible with Raspberry Pi 'spi1-1cs' hats. + ### forlinx-ok3506-s12-spi0-1cs-spidev Enables SPI0 spidev on forlinx-ok3506-s12 with one chipselect. Compatible with Raspberry Pi 'spi0-1cs' hats. diff --git a/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-1cs-spidev.dts b/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-1cs-spidev.dts new file mode 100644 index 0000000000000..159656570793b --- /dev/null +++ b/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-1cs-spidev.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Enable spidev on SPI0 with RM_IO pinmux at RPi SPI0 physical positions: + * MOSI = RM_IO9 (pin 19), MISO = RM_IO10 (pin 21), + * CLK = RM_IO8 (pin 23), CS0 = RM_IO14 (pin 24) + * Compatible with Raspberry Pi 'spi0-1cs' hats + */ + +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SPI0 spidev on ebyte-ecb41-pge"; + compatible = "ebyte,ecb41-pge"; + category = "spi"; + exclusive = "spi0", "RM_IO8", "RM_IO9", "RM_IO10", "RM_IO14"; + description = "Enable SPI0 spidev using RM_IO9(MOSI), RM_IO10(MISO), RM_IO8(CLK), RM_IO14(CS0)."; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io8_spi0_clk &rm_io10_spi0_miso &rm_io9_spi0_mosi &rm_io14_spi0_csn0>; + + spi@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-2cs-spidev.dts b/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-2cs-spidev.dts new file mode 100644 index 0000000000000..8ccbc6b31bce2 --- /dev/null +++ b/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi0-2cs-spidev.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Enable spidev on SPI0 with RM_IO pinmux at RPi SPI0 physical positions: + * MOSI = RM_IO9 (pin 19), MISO = RM_IO10 (pin 21), + * CLK = RM_IO8 (pin 23), CS0 = RM_IO14 (pin 24), CS1 = RM_IO7 (pin 26) + * Compatible with Raspberry Pi 'spi0-2cs' hats + */ + +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SPI0 spidev on ebyte-ecb41-pge with two chipselects"; + compatible = "ebyte,ecb41-pge"; + category = "spi"; + exclusive = "spi0", "RM_IO7", "RM_IO8", "RM_IO9", "RM_IO10", "RM_IO14"; + description = "Enable SPI0 spidev using RM_IO9(MOSI), RM_IO10(MISO), RM_IO8(CLK), RM_IO14(CS0), RM_IO7(CS1)."; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io8_spi0_clk &rm_io10_spi0_miso &rm_io9_spi0_mosi &rm_io14_spi0_csn0 &rm_io7_spi0_csn1>; + + spi@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + status = "okay"; + }; + + spi@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi1-1cs-spidev.dts b/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi1-1cs-spidev.dts new file mode 100644 index 0000000000000..c7c84204976a9 --- /dev/null +++ b/arch/arm/boot/dts/overlay/rockchip-ebyte-ecb41-pge-spi1-1cs-spidev.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Enable spidev on SPI1 with RM_IO pinmux at RPi SPI1 physical positions: + * MOSI = RM_IO0 (pin 38), MISO = RM_IO11 (pin 35), + * CLK = RM_IO1 (pin 40), CS0 = RM_IO12 (pin 12) + * Compatible with Raspberry Pi 'spi1-1cs' hats + */ + +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SPI1 spidev on ebyte-ecb41-pge"; + compatible = "ebyte,ecb41-pge"; + category = "spi"; + exclusive = "spi1", "RM_IO0", "RM_IO1", "RM_IO11", "RM_IO12"; + description = "Enable SPI1 spidev using RM_IO0(MOSI), RM_IO11(MISO), RM_IO1(CLK), RM_IO12(CS0)."; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io1_spi1_clk &rm_io11_spi1_miso &rm_io0_spi1_mosi &rm_io12_spi1_csn0>; + + spi@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/rk3506g-ebyte-ecb41-pge.dts b/arch/arm/boot/dts/rk3506g-ebyte-ecb41-pge.dts index 5c8ed6cd13663..842d8833ae866 100644 --- a/arch/arm/boot/dts/rk3506g-ebyte-ecb41-pge.dts +++ b/arch/arm/boot/dts/rk3506g-ebyte-ecb41-pge.dts @@ -177,7 +177,7 @@ }; &cma { - size = <0x400000>; + size = <0x800000>; }; &cpu0 { From 5466f804d92b9b0d15ddf3ddb60fbdd3de9c12a5 Mon Sep 17 00:00:00 2001 From: JSQ <116248144+ifroncy01@users.noreply.github.com> Date: Thu, 28 May 2026 03:29:33 +0800 Subject: [PATCH 08/32] arm64:dts:rockchip:rk3568/rk3588:Add EasePi A2 (RK3568) and EasePi R2 (RK3588) board support (#486) * easepi-a2, easepi-r2: add device tree support for vendor kernel 6.1 Add board device tree files for EasePi A2 (RK3568) and EasePi R2 (RK3588): - rk3568-easepi-a2.dts: Board DTS for EasePi A2, includes shared carrier board definition rk3568-roc-k40pro.dtsi - rk3568-roc-k40pro.dtsi: Shared hardware config for the ROC-RK3568-PC carrier platform (PMIC, regulators, GPIO, etc.) - rk3588-easepi-r2.dts: Board DTS for EasePi R2, self-contained with includes for rk3588-rk806-single.dtsi and rk3588-linux.dtsi Signed-off-by: ifroncy01 * easepi-a2: Merge roc-k40pro.dtsi into standalone DTS Combine rk3568-roc-k40pro.dtsi carrier board config into rk3568-easepi-a2.dts, making it self-contained: - Merge full root node hardware description (PMIC, regulators, leds) - Apply easepi-a2 specific root node properties - Replace ethernet aliases to use pcie_eth0 - Append all easepi-a2 label overrides (gmac0/1 disabled, pcie enabled, etc.) - Remove rk3568-roc-k40pro.dtsi as it is no longer needed * easepi-a2: fix DTC pci_device_reg warning Change PCIe bridge node address from pcie@10 to pcie@10,0 to follow standard PCI device tree address format (device,function). * easepi-a2: fix pci_device_reg DTS warning Change PCIe bridge node address from pcie@10 to pcie@10,0 to follow standard PCI device tree address format (device,function). Fixes a DTS warning: Warning (pci_device_reg): /pcie@fe260000/pcie@10: PCI unit address format error, expected "0,0" * easepi: various DTS fixes and cleanups For easepi-a2: - Fix adc-keys press-threshold-microvolt from 1750 to 175000 - Disable rk809-sound (audio card not present on board) - Formatting fix on i2s1_8ch pinctrl indentation - Translate Chinese comments to English For easepi-r2: - Fix compatible string to "easepi,r2" - Fix comment formatting and translate Chinese comments to English - Fix sdio status placement * easepi-a2: DTS fix --------- Signed-off-by: ifroncy01 --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3568-easepi-a2.dts | 1245 +++++++++++++++++ .../boot/dts/rockchip/rk3588-easepi-r2.dts | 1038 ++++++++++++++ 3 files changed, 2285 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d13871fde1aee..9d7be7dd1d0f6 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -212,6 +212,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-a2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-hnas.dtb @@ -379,6 +380,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-rk628-hdmi2csi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-aim7-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-easepi-r2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-cyber-aib.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-fxblox-rk1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts b/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts new file mode 100644 index 0000000000000..4bc9ce432e9f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts @@ -0,0 +1,1245 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + compatible = "easepi,a2", "rockchip,rk3568"; + model = "EasePi A2"; + kdebug = "0"; + hwmodel_id = "A2"; + hw_support = "hdmi"; + eth_order = "0000:01:00.0"; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + + ethernet0 = &pcie_eth0; + /delete-property/ ethernet1; + + led-boot = &led_green; + led-failsafe = &led_green; + led-running = &led_green; + led-upgrade = &led_green; + }; + + chosen: chosen { + power-key-factory-reset; + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 rootpart=mmcblk1p3 rw rootwait autoresize=mmcblk1p4"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <175000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec 0>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + WIFI,poweren_gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_green_en>; + + led_green: green { + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + label = "green:sys"; + linux,default-trigger = "heartbeat"; + }; + + }; + + vcc3v3_nvme: vcc3v3-nvme-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_nvme"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&dc_12v>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_nvme_en>; + }; + +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + realtek,led-data = <0xAC10>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + realtek,led-data = <0xAC10>; + }; +}; + +&combphy0_us { + rockchip,dis-u3otg0-port; /* disable USB3.0 */ + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; +}; + +&gpu { + power-off-delay-ms = <200>; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc3v3_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "disabled"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + leds { + led_green_en: led-green-en { + rockchip,pins = + <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + /* + led_yellow_en: led-yellow-en { + rockchip,pins = + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_blue_en: led-blue-en { + rockchip,pins = + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + */ + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&pwm5 { + status = "disabled"; +}; + +&pwm7 { + status = "disabled"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; +}; + +&reserved_memory { + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 0x10000000 0x0 0x00800000>; + linux,cma-default; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&pcie2x1 { + status = "disabled"; +}; + +&pcie30phy { + status = "okay"; +}; + + +&pcie3x1 { + rockchip,bifurcation; + status = "okay"; + +}; + +&pcie3x2 { + rockchip,bifurcation; + status = "okay"; +}; + + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + support-multi-area; +}; + +&vop_mmu { + status = "okay"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +// Configure WL_REG_ON pin +&sdio_pwrseq { + status = "okay"; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; +}; + +// Configure WL_HOST_WAKE pin, required for OOB mode +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + wifi_chip_type = "ap6255"; + status = "okay"; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +// WiFi +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +/* fix mali warning */ +&gpu { + power-off-delay-ms = <200>; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pcie@10 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + pcie_eth0: pcie-eth@10,0 { + compatible = "pci10ec,8125"; + reg = <0x000000 0 0 0 0>; + + realtek,led-data = <0 0 0x200 0x02B>; + realtek,led-feature = /bits/ 8 <0xC0>; + }; + }; +}; + +&pcie3x1 { + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_nvme>; + status = "okay"; + +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_nvme>; + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "disabled"; +}; + +&usbdrd30 { + status = "disabled"; +}; + +&pinctrl { + nvme { + vcc3v3_nvme_en: vcc3v3-nvme-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + oled { + oled_en: oled-en { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&led_green { + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; +}; + +&led_green_en { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m1_xfer &oled_en>; + + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + status = "okay"; +}; + +&adc_keys { + vol-up-key { + label = "recovery"; + linux,code = ; + }; +}; + +// Bluetooth +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +// IR receiver +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts new file mode 100644 index 0000000000000..a1a2eb17f0eb7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts @@ -0,0 +1,1038 @@ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" +#include "rk3588-rk806-single.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "EasePi R2"; + compatible = "easepi,r2", "rockchip,rk3588"; + eth_order = "0004:41:00.0,0002:21:00.0,0001:11:00.0,0003:31:00.0"; + + aliases { + led-boot = &led_red; + led-failsafe = &led_red; + led-running = &led_red; + led-upgrade = &led_red; + + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &sdhci; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_en>; + + led_red: work { + label = "red:work"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc3v0_sys: vcc3v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sys"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc4v0_sys: vcc4v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-name = "vcc4v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; + + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_05: vcc3v3-pi6c-05 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c_05"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + pinctrl-names = "default"; + pinctrl-0 = <&pi6c_power_en>; + vin-supply = <&vcc4v0_sys>; + }; + + /* actually fed by vcc_3v3_s3, dependent on pi6c clock generator */ + vcc3v3_pcie: vcc3v3-pcie { + //compatible = "regulator-fixed-clock"; + //clocks = <&pcie30_refclk>; + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie"; + startup-delay-us = <50000>; + vin-supply = <&vcc_3v3_s3>; + }; + + /* actually fed by vcc12v_dcin, dependent on pi6c clock generator */ + vcc3v3_m2: vcc3v3-m2 { + //compatible = "regulator-fixed-clock"; + //clocks = <&pcie30_refclk>; + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_m2"; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vdd0v95_25glan1: vdd0v95-25glan1 { + compatible = "regulator-fixed"; + regulator-name = "vdd0v95_25glan1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd0v95_25glan1_en>; + vin-supply = <&vcc_3v3_s3>; + }; + vdd0v95_25glan2: vdd0v95-25glan2 { + compatible = "regulator-fixed"; + regulator-name = "vdd0v95_25glan2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd0v95_25glan2_en>; + vin-supply = <&vcc_3v3_s3>; + }; + vdd0v95_25glan3: vdd0v95-25glan3 { + compatible = "regulator-fixed"; + regulator-name = "vdd0v95_25glan3"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd0v95_25glan3_en>; + vin-supply = <&vcc_3v3_s3>; + }; + vdd0v95_25glan4: vdd0v95-25glan4 { + compatible = "regulator-fixed"; + regulator-name = "vdd0v95_25glan4"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd0v95_25glan4_en>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v8_modem: vcc3v8-modem { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-name = "vcc3v8_modem"; + pinctrl-names = "default"; + pinctrl-0 = <&modem_power_en>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_usb: vbus5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_usb_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vbus5v0_usb"; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;// schematic wrongly connected to GPIO4_C3 + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9m0_gpios>; + BT,reset_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwren>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_sd"; + vin-supply = <&vcc_3v3_s3>; + }; + + fan0: gpio_fan0 { + compatible = "gpio-fan"; + fan-supply = <&vcc12v_dcin>; + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = + < 0 0>, + <2500 1>; + pinctrl-names = "default"; + pinctrl-0 = <&fan0_en_h>; + #cooling-cells = <2>; + }; + + fan1: gpio_fan1 { + compatible = "gpio-fan"; + fan-supply = <&vcc12v_dcin>; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = + < 0 0>, + <2500 1>; + pinctrl-names = "default"; + pinctrl-0 = <&fan1_en_h>; + #cooling-cells = <2>; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x00 0x10000000 0x00 0x8000000>; + size = <0x00 0x800000>; + linux,cma-default; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&crypto { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-compatible = "rk860x-reg"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + }; +}; + +&pcie2x1l0 { + // idx3,p0l1 => rtl8125 + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + phys = <&pcie30phy>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie2x1l1 { + // idx4, p1l1 => rtl8125 + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + phys = <&pcie30phy>; + reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +// combphy0_ps -> pcie2x1l2 +&pcie2x1l2 { + // rtl8125 + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + data-lanes = <1 3 2 4>; + status = "okay"; +}; + +&pcie3x2 { + // idx2, p1l0 => rtl8125 + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x4 { + // idx1, p0l0 => nvme + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + num-lanes = <1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2>; + status = "okay"; +}; + +&pinctrl { + rtl8211f { + rtl8211f0_rst: rtl8211f0-rst { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rtl8211f1_rst: rtl8211f1-rst { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + leds { + led_work_en: led_work_en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + modem { + modem_power_en: modem-power-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie-nics { + vdd0v95_25glan1_en: vdd0v95-25glan1-en { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vdd0v95_25glan2_en: vdd0v95-25glan2-en { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vdd0v95_25glan3_en: vdd0v95-25glan3-en { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vdd0v95_25glan4_en: vdd0v95-25glan4-en { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pi6c { + pi6c_power_en: pi6c-power-en { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + power { + vcc3v3_power_en: vcc3v3_power_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + sdmmc { + sd_pwren: sd-pwren { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { + vbus5v0_usb_en: vbus5v0_usb_en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart9m0_gpios: uart9m0-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + fan { + fan0_en_h: fan0-en-h { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + fan1_en_h: fan1-en-h { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +// IR receiver +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +// WiFi SDIO +&sdio { + pinctrl-0 = <&sdiom0_pins>; + max-frequency = <150000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr50; + sd-uhs-sdr104; // SDIO 3.0 + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m2_xfer>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled";// Use FIQ debugger instead of UART2 +}; + +&uart3 { + pinctrl-0 = <&uart3m2_xfer>; + status = "okay"; +}; + +// Bluetooth +&uart9 { + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; + status = "okay"; +}; + +// Type-C for firmware update +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + extcon = <&u2phy0>; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +// USB 3.0 +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vbus5v0_usb>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1>; + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + + +// 4G modem +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc3v8_modem>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +// USB 2.0 +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vbus5v0_usb>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +// VPU/NPU/GPU + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +// HDMI TX +&i2s5_8ch { + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +// HDMI RX +&i2s7_8ch { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; From d637729f1e0aa4b706039c597ee29269beb8c315 Mon Sep 17 00:00:00 2001 From: mingzhangqun Date: Thu, 28 May 2026 17:40:46 +0800 Subject: [PATCH 09/32] arm64: dts: rockchip: rk3576: remove empty rockchip,supported-hw from OPP tables (#484) * arm64: dts: rockchip: rk3576: remove empty rockchip,supported-hw from OPP tables The bare "rockchip,supported-hw;" property with no value makes the OPP framework require opp-supported-hw on every OPP entry, but only opp-j-m-* entries have it. This causes all generic OPP entries to be rejected, resulting in GPU stuck at a fixed ~100 MHz without devfreq. Remove the empty property so standard opp-* entries are always available for non-J/M chips. Affects: cluster0, cluster1, bus_a72, dmc, npu, gpu, vop OPP tables. Signed-off-by: mingzq * arm64: dts: rockchip: keep rk3576 supported-hw outside GPU --------- Signed-off-by: mingzq --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 68ef16ab55361..42efd780cd336 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -2689,7 +2689,6 @@ nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>; nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; - rockchip,supported-hw; rockchip,pvtm-hw = <0x06>; rockchip,pvtm-voltage-sel-hw = < From 2310b5c1105145b16422bb270956d76543c6126b Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Thu, 28 May 2026 13:24:57 +0800 Subject: [PATCH 10/32] easepi-r2: sync device tree with latest code PR #486 is based on the v1.0 board, but the actual board sold is v1.2. Changes in v1.2: 1. Remove power supply control for the TF card to support booting from the TF card. 2. Remove power supply control for the PI6C clock, now it's directly powered. 3. Export the I2C7 pinout. Signed-off-by: Liangbin Lian --- .../boot/dts/rockchip/rk3588-easepi-r2.dts | 175 ++++++++---------- 1 file changed, 80 insertions(+), 95 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts index a1a2eb17f0eb7..abe02057bf959 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts @@ -12,29 +12,30 @@ / { model = "EasePi R2"; - compatible = "easepi,r2", "rockchip,rk3588"; - eth_order = "0004:41:00.0,0002:21:00.0,0001:11:00.0,0003:31:00.0"; + compatible = "linkease,easepi-r2", "easepi,r2", "rockchip,rk3588"; aliases { - led-boot = &led_red; - led-failsafe = &led_red; - led-running = &led_red; - led-upgrade = &led_red; + led-boot = &led_run; + led-failsafe = &led_run; + led-running = &led_run; + led-upgrade = &led_run; mmc0 = &sdmmc; mmc1 = &sdio; mmc2 = &sdhci; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_work_en>; + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1750000>; + poll-interval = <100>; - led_red: work { - label = "red:work"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + button-maskrom { + label = "Mask Rom"; + linux,code = ; + press-threshold-microvolt = <878>; }; }; @@ -87,26 +88,20 @@ vin-supply = <&vcc5v0_sys>; }; - /* pi6c pcie clock generator feeds both ports */ - vcc3v3_pi6c_05: vcc3v3-pi6c-05 { + vcc3v3_nvme: vcc3v3-nvme { compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pi6c_05"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_nvme"; + vin-supply = <&vcc12v_dcin>; enable-active-high; gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; startup-delay-us = <5000>; pinctrl-names = "default"; - pinctrl-0 = <&pi6c_power_en>; - vin-supply = <&vcc4v0_sys>; + pinctrl-0 = <&nvme_power_en>; }; - /* actually fed by vcc_3v3_s3, dependent on pi6c clock generator */ vcc3v3_pcie: vcc3v3-pcie { - //compatible = "regulator-fixed-clock"; - //clocks = <&pcie30_refclk>; compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -115,18 +110,6 @@ vin-supply = <&vcc_3v3_s3>; }; - /* actually fed by vcc12v_dcin, dependent on pi6c clock generator */ - vcc3v3_m2: vcc3v3-m2 { - //compatible = "regulator-fixed-clock"; - //clocks = <&pcie30_refclk>; - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_m2"; - startup-delay-us = <50000>; - vin-supply = <&vcc12v_dcin>; - }; - vdd0v95_25glan1: vdd0v95-25glan1 { compatible = "regulator-fixed"; regulator-name = "vdd0v95_25glan1"; @@ -206,19 +189,6 @@ vin-supply = <&vcc5v0_sys>; }; - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;// schematic wrongly connected to GPIO4_C3 - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart9m0_gpios>; - BT,reset_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - }; - wireless_wlan: wireless-wlan { compatible = "wlan-platdata"; wifi_chip_type = "ap6255"; @@ -237,19 +207,6 @@ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; - vcc3v3_sd: vcc3v3-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pwren>; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "vcc3v3_sd"; - vin-supply = <&vcc_3v3_s3>; - }; - fan0: gpio_fan0 { compatible = "gpio-fan"; fan-supply = <&vcc12v_dcin>; @@ -301,7 +258,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ cma { compatible = "shared-dma-pool"; @@ -311,6 +268,22 @@ linux,cma-default; }; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_run_en>, <&led_user_en>; + + led_run: led-0 { + label = "green:run"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + led-1 { + label = "green:user"; + gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + }; + }; }; &combphy0_ps { @@ -436,8 +409,14 @@ }; }; +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; +}; + &pcie2x1l0 { - // idx3,p0l1 => rtl8125 + // pcie30phy lane3, p0l1, 0002:20:00.0 => rtl8125 (lan1,eth1) pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>; phys = <&pcie30phy>; @@ -447,7 +426,7 @@ }; &pcie2x1l1 { - // idx4, p1l1 => rtl8125 + // pcie30phy lane4, p1l1, 0003:30:00.0 => rtl8125 (lan3,eth3) pinctrl-names = "default"; pinctrl-0 = <&pcie2_1_rst>; phys = <&pcie30phy>; @@ -456,9 +435,8 @@ status = "okay"; }; -// combphy0_ps -> pcie2x1l2 &pcie2x1l2 { - // rtl8125 + // combphy0_ps, 0004:40:00.0 => rtl8125 (lan4,eth0) pinctrl-names = "default"; pinctrl-0 = <&pcie2_2_rst>; reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; @@ -467,13 +445,14 @@ }; &pcie30phy { + // divided into 4 lanes rockchip,pcie30-phymode = ; data-lanes = <1 3 2 4>; status = "okay"; }; &pcie3x2 { - // idx2, p1l0 => rtl8125 + // pcie30phy lane2, p1l0, 0001:10:00.0 => rtl8125 (lan2,eth2) pinctrl-names = "default"; pinctrl-0 = <&pcie3x2_rst>; num-lanes = <1>; @@ -483,33 +462,28 @@ }; &pcie3x4 { - // idx1, p0l0 => nvme + // pcie30phy lane1, p0l0, 0000:00:00.0 => nvme pinctrl-names = "default"; pinctrl-0 = <&pcie3x4_rst>; num-lanes = <1>; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_m2>; + vpcie3v3-supply = <&vcc3v3_nvme>; status = "okay"; }; &pinctrl { - rtl8211f { - rtl8211f0_rst: rtl8211f0-rst { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - rtl8211f1_rst: rtl8211f1-rst { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; hdmirx { hdmirx_det: hdmirx-det { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; leds { - led_work_en: led_work_en { + led_run_en: led_run_en { rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; + led_user_en: led_user_en { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; modem { @@ -552,8 +526,8 @@ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - pi6c { - pi6c_power_en: pi6c-power-en { + nvme { + nvme_power_en: nvme-power-en { rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -567,11 +541,6 @@ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - sdmmc { - sd_pwren: sd-pwren { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; usb { vbus5v0_usb_en: vbus5v0_usb_en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -579,12 +548,6 @@ }; - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - wireless-bluetooth { uart9m0_gpios: uart9m0-gpios { rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; @@ -651,6 +614,7 @@ status = "okay"; }; +// eMMC &sdhci { bus-width = <8>; no-sdio; @@ -662,6 +626,7 @@ status = "okay"; }; +// TF Card slot &sdmmc { max-frequency = <150000000>; no-sdio; @@ -671,7 +636,7 @@ cap-sd-highspeed; disable-wp; sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; + vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vccio_sd_s0>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; @@ -679,7 +644,7 @@ }; // WiFi SDIO -&sdio { +&sdio { pinctrl-0 = <&sdiom0_pins>; max-frequency = <150000000>; no-sd; @@ -720,8 +685,27 @@ // Bluetooth &uart9 { - pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn &uart9m0_rtsn>; status = "okay"; + uart-has-rtscts; + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + /* + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wakeup"; + */ + host-wakeup-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reset_gpio &bt_wake_gpio &bt_irq_gpio>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; }; // Type-C for firmware update @@ -730,6 +714,7 @@ }; &u2phy0_otg { + rockchip,typec-vbus-det; status = "okay"; }; From 6475fed933852b75452da974c7376b6648dafed8 Mon Sep 17 00:00:00 2001 From: mingzhangqun Date: Fri, 29 May 2026 02:13:42 +0800 Subject: [PATCH 11/32] arm64: dts: rockchip: fix adc-keys press-threshold-microvolt for recomputer devkits (#483) The volumeup-key press-threshold-microvolt was set to 1750 instead of 1750000 (1.75V), off by a factor of 1000. Fix for both rk3576 and rk3588 recomputer devkit boards. --- .../arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts | 2 +- .../arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts b/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts index 5b2f6638c9ea5..928b837726c7d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-recomputer-rk3576-devkit.dts @@ -34,7 +34,7 @@ volumeup-key { linux,code = ; label = "volume up"; - press-threshold-microvolt = <1750>; + press-threshold-microvolt = <1750000>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts b/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts index 70491bb9d2b69..918c7c3430de1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts @@ -37,7 +37,7 @@ volumeup-key { linux,code = ; label = "volume up"; - press-threshold-microvolt = <1750>; + press-threshold-microvolt = <1750000>; }; }; From 1db1cfa8327f71cc15e78dda6722c3d5d060ef26 Mon Sep 17 00:00:00 2001 From: Stepan Mazurov Date: Thu, 28 May 2026 12:47:42 -0600 Subject: [PATCH 12/32] media: rockchip: hdmirx: add DT-driven edid-version + set 600M for OPi5U (#488) * media: rockchip: hdmirx: add edid version to disable NV24 Add two new EDID variants (HDMIRX_EDID_340M_NV12 = 3 and HDMIRX_EDID_600M_NV12 = 4) that omit the YCbCr 4:4:4 (NV24) capability bit and let the driver fix up the EDID checksum accordingly. Read the selected variant from the new `edid-version` DT property on the hdmirx_ctrler node so per-board defaults can be chosen without requiring userspace to poke the edid sysfs file at boot. This is a direct prerequisite for board DTS files that want to advertise a default EDID other than the hard-coded 340MHz variant. Signed-off-by: jensen [smazurov@gmail.com: cherry-picked unmodified from friendlyarm/kernel-rockchip commit ee391fb22 on branch nanopi6-v6.1.y. Applies cleanly on top of armbian/linux-rockchip rk-6.1-rkr5.1 (with offsets, due to subsequent unrelated drift). Tested on Orange Pi 5 Ultra (RK3588) with both 1080p60 and 4K60 HDMI sources; required by the companion DTS patch which sets edid-version = <2> for OPi5U.] Tested-by: Stepan Mazurov Signed-off-by: Stepan Mazurov * arm64: dts: rockchip: opi5-ultra: default hdmirx edid-version to 600M Set edid-version = <2> (HDMIRX_EDID_600M) on the hdmirx_ctrler node so the default EDID advertised to upstream HDMI sources includes the TMDS-up-to-600MHz block (covering 4K@60 modes), instead of the driver's built-in HDMIRX_EDID_340M default which advertises only up to TMDS 340MHz (1080p60 / 4K@30). Symptom without this property on Orange Pi 5 Ultra: a 4K-capable HDMI source (tested with a Linux desktop pushing 3840x2160@60 from a discrete GPU) cycles indefinitely between TMDS-valid and TMDS-invalid states. The hdmirx PHY rejects the source's 4K stream because the EDID the source read did not advertise 4K support, yet the source insists on 4K based on its own display configuration. Writing "2" to /sys/devices/platform/fdee0000.hdmirx-controller/hdmirx/hdmirx/edid at runtime resolves the symptom immediately and stably; this DTS change makes the runtime fix the default at boot. The Rock 5B+ and NanoPC-T6 board DTS files already set similar edid-version properties; Orange Pi 5 Ultra was missing the equivalent. Depends on the rk_hdmirx driver reading edid-version from DT (prerequisite patch: cherry-pick of friendlyarm/kernel-rockchip commit ee391fb22 in the companion patch). Tested-by: Stepan Mazurov Signed-off-by: Stepan Mazurov --------- Signed-off-by: jensen Signed-off-by: Stepan Mazurov Co-authored-by: jensen --- .../dts/rockchip/rk3588-orangepi-5-ultra.dts | 1 + .../platform/rockchip/hdmirx/rk_hdmirx.c | 48 ++++++++++++++++--- 2 files changed, 43 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts index 9e88c6d40b447..a15116058d0cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts @@ -1400,6 +1400,7 @@ /* Should work with at least 128MB cma reserved above. */ &hdmirx_ctrler { #sound-dai-cells = <1>; + edid-version = <2>; /* Effective level used to trigger HPD: 0-low, 1-high */ hpd-trigger-level = <1>; hdmirx-det-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c index 1370b7e6f47e1..a2ec7fc6c97ab 100644 --- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c +++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c @@ -148,6 +148,8 @@ enum hdmirx_edid_version { HDMIRX_EDID_USER = 0, HDMIRX_EDID_340M = 1, HDMIRX_EDID_600M = 2, + HDMIRX_EDID_340M_NV12 = 3, + HDMIRX_EDID_600M_NV12 = 4, }; struct hdmirx_reg_table { @@ -4003,7 +4005,6 @@ static int hdmirx_parse_dt(struct rk_hdmirx_dev *hdmirx_dev) return PTR_ERR(hdmirx_dev->rst_biu); } - hdmirx_dev->hdmirx_det_gpio = devm_gpiod_get_optional(dev, "hdmirx-det", GPIOD_IN); if (IS_ERR(hdmirx_dev->hdmirx_det_gpio)) { @@ -4039,6 +4040,8 @@ static int hdmirx_parse_dt(struct rk_hdmirx_dev *hdmirx_dev) if (of_property_read_bool(np, "cec-enable")) hdmirx_dev->cec_enable = true; + of_property_read_u32(np, "edid-version", &hdmirx_dev->edid_version); + ret = of_reserved_mem_device_init(dev); if (ret) dev_warn(dev, "No reserved memory for HDMIRX, use default CMA\n"); @@ -4098,19 +4101,51 @@ static int hdmirx_power_on(struct rk_hdmirx_dev *hdmirx_dev) return 0; } +static void hdmirx_fixup_edid(struct rk_hdmirx_dev *hdmirx_dev, + u8 *edid, int edid_len) +{ + int i; + u8 sum; + + /* CTA Extension data format */ +#define EDID_CEA_YCRCB444 (1 << 5) + + if (hdmirx_dev->edid_version == HDMIRX_EDID_340M || + hdmirx_dev->edid_version == HDMIRX_EDID_600M) + edid[131] |= EDID_CEA_YCRCB444; + else + edid[131] &= ~EDID_CEA_YCRCB444; + + /* update checksum */ + for (i = 0, sum = 0; i < edid_len - 1; i++) + sum += edid[i]; + + edid[i] = 0x100 - sum; +} + static void hdmirx_edid_init_config(struct rk_hdmirx_dev *hdmirx_dev) { int ret; struct v4l2_edid def_edid; + u8 *edid_data; + int edid_len; /* disable hpd and write edid */ def_edid.pad = 0; def_edid.start_block = 0; def_edid.blocks = EDID_NUM_BLOCKS_MAX; - if (hdmirx_dev->edid_version == HDMIRX_EDID_600M) - def_edid.edid = edid_init_data_600M; - else - def_edid.edid = edid_init_data_340M; + + if (hdmirx_dev->edid_version == HDMIRX_EDID_600M || + hdmirx_dev->edid_version == HDMIRX_EDID_600M_NV12) { + edid_data = edid_init_data_600M; + edid_len = sizeof(edid_init_data_600M); + } else { + edid_data = edid_init_data_340M; + edid_len = sizeof(edid_init_data_340M); + } + hdmirx_fixup_edid(hdmirx_dev, edid_data, edid_len); + + def_edid.edid = edid_data; ret = hdmirx_write_edid(hdmirx_dev, &def_edid, false); if (ret) dev_err(hdmirx_dev->dev, "%s write edid failed!\n", __func__); @@ -4244,7 +4279,8 @@ static ssize_t edid_store(struct device *dev, if (kstrtoint(buf, 10, &edid)) return -EINVAL; - if (edid != HDMIRX_EDID_340M && edid != HDMIRX_EDID_600M) + if (edid != HDMIRX_EDID_340M && edid != HDMIRX_EDID_340M_NV12 && + edid != HDMIRX_EDID_600M && edid != HDMIRX_EDID_600M_NV12) return count; if (hdmirx_dev->edid_version != edid) { From 60ffebcdbb8f486cab5efcaf93964811ffb6f483 Mon Sep 17 00:00:00 2001 From: mingzhangqun Date: Fri, 29 May 2026 17:51:56 +0800 Subject: [PATCH 13/32] arm64: dts: rockchip: add vpll clock parent for DP 4K overlay (#490) Signed-off-by: mingzq --- .../overlay/recomputer-rk3576-devkit-dp-4k.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/overlay/recomputer-rk3576-devkit-dp-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/recomputer-rk3576-devkit-dp-4k.dts index 8051a522962dc..f865250a1bec7 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/recomputer-rk3576-devkit-dp-4k.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/recomputer-rk3576-devkit-dp-4k.dts @@ -1,12 +1,14 @@ /dts-v1/; /plugin/; +#include + / { metadata { title = "Route recomputer rk3576 devkit HDMI to VP1 and DP to VP0"; compatible = "seeed,recomputer rk3576 devkit"; category = "display"; - description = "Switch display routing so HDMI uses VP1 and DP uses VP0."; + description = "Switch display routing so HDMI uses VP1 and DP uses VP0. Sets dclk_vp0_src parent to vpll for 4K@60Hz pixel clock support."; }; fragment@0 { @@ -69,4 +71,17 @@ target = <&vp1>; __overlay__ { status = "okay"; }; }; + + /* Set dclk_vp0_src parent to vpll so DP on VP0 can achieve 4K@60Hz. + * Without this, DP falls back to gpll/cpll which can only provide + * ~396MHz (via divider), far below the 533.25MHz needed for 4K@60Hz. + * With vpll, the driver reprograms vpll to 1066.5MHz and divides by 2. + */ + fragment@11 { + target = <&vop>; + __overlay__ { + assigned-clocks = <&cru DCLK_VP0_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; + }; + }; }; From 9b27bcd0ac34d16fa4df2269eb5ee4ade8a17071 Mon Sep 17 00:00:00 2001 From: mingzhangqun Date: Mon, 1 Jun 2026 18:57:30 +0800 Subject: [PATCH 14/32] drm: rockchip: DSI fixes for RK3576 dual-display (#495) --- .../gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 4 ++++ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index c56bec9c08221..add2543022f66 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -1497,6 +1497,10 @@ static int dw_mipi_dsi2_connector_init(struct dw_mipi_dsi2 *dsi2) drm_connector_helper_add(connector, &dw_mipi_dsi2_connector_helper_funcs); + + if (dsi2->panel) + drm_connector_set_orientation_from_panel(connector, dsi2->panel); + ret = drm_connector_attach_encoder(connector, encoder); if (ret < 0) { DRM_DEV_ERROR(dev, "Failed to attach encoder: %d\n", ret); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index fe4c7fe9ba698..10a6df4002ecc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -10226,6 +10226,25 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta ret = vop2_clk_set_parent_extend(vp, vcstate, true); if (ret < 0) goto out; + + /* + * For RK3576 MIPI/DSI output, switch dclk_src parent from vpll + * to cpll. This prevents DP's vpll reprogramming from breaking + * DSI pixel clock when both displays are active. + * cpll at 1000MHz supports 720x1280@60 exactly (1000/12=83.33MHz). + */ + if (vop2->version == VOP_VERSION_RK3576 && + (vcstate->output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_MIPI1))) { + struct clk_hw *dclk_hw = __clk_get_hw(vp->dclk); + if (dclk_hw) { + struct clk_hw *src_hw = clk_hw_get_parent(dclk_hw); + if (src_hw) { + struct clk *cpll = __clk_lookup("cpll"); + if (cpll) + clk_set_parent(src_hw->clk, cpll); + } + } + } if (dclk) dclk_rate = dclk->rate; else From 5e85ac92521983512536de805db36dee1bfff8fd Mon Sep 17 00:00:00 2001 From: jjm2473 Date: Fri, 29 May 2026 11:57:38 +0800 Subject: [PATCH 15/32] easepi-r2: fix kernel cmdline 'root=' overridden by device tree which cause initramfs load rootfs failed Signed-off-by: Liangbin Lian --- arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts index abe02057bf959..79b001721ebcc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts @@ -25,6 +25,8 @@ mmc2 = &sdhci; }; + /delete-node/ chosen; + adc-keys-0 { compatible = "adc-keys"; io-channels = <&saradc 0>; From 8ccf5fb701e1fbd63ba0458415082f465ad3ac21 Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Fri, 29 May 2026 20:50:21 +0800 Subject: [PATCH 16/32] easepi-r2: IR receiver use gpio-ir-receiver driver Signed-off-by: Liangbin Lian --- arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts index 79b001721ebcc..f3d1bb4fd8134 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-easepi-r2.dts @@ -209,6 +209,13 @@ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + fan0: gpio_fan0 { compatible = "gpio-fan"; fan-supply = <&vcc12v_dcin>; @@ -592,7 +599,7 @@ }; }; -// IR receiver +// IR receiver, but we use gpio-ir-receiver driver &pwm3 { compatible = "rockchip,remotectl-pwm"; pinctrl-names = "default"; @@ -600,7 +607,7 @@ remote_pwm_id = <3>; handle_cpu_id = <1>; remote_support_psci = <0>; - status = "okay"; + status = "disabled"; }; &saradc { From 7e1e514ac302005e19baac239bc123a126f1f1a8 Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Fri, 29 May 2026 21:06:21 +0800 Subject: [PATCH 17/32] easepi-a2: IR receiver use gpio-ir-receiver driver Signed-off-by: Liangbin Lian --- .../arm64/boot/dts/rockchip/rk3568-easepi-a2.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts b/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts index 4bc9ce432e9f6..1fd50e47d97dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts @@ -275,6 +275,13 @@ status = "okay"; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -786,6 +793,11 @@ }; &pinctrl { + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; leds { led_green_en: led-green-en { rockchip,pins = @@ -1233,7 +1245,7 @@ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; }; -// IR receiver +// IR receiver, but we use gpio-ir-receiver driver &pwm3 { compatible = "rockchip,remotectl-pwm"; pinctrl-names = "default"; @@ -1241,5 +1253,5 @@ remote_pwm_id = <3>; handle_cpu_id = <1>; remote_support_psci = <0>; - status = "okay"; + status = "disabled"; }; From 713542620f7c9c6287ef11487748e7bae13a63df Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Sun, 31 May 2026 11:56:25 +0800 Subject: [PATCH 18/32] easepi-a2: clean up device tree Signed-off-by: Liangbin Lian --- .../boot/dts/rockchip/rk3568-easepi-a2.dts | 106 +----------------- 1 file changed, 6 insertions(+), 100 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts b/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts index 1fd50e47d97dd..307895bec344c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-a2.dts @@ -18,10 +18,6 @@ / { compatible = "easepi,a2", "rockchip,rk3568"; model = "EasePi A2"; - kdebug = "0"; - hwmodel_id = "A2"; - hw_support = "hdmi"; - eth_order = "0000:01:00.0"; aliases { mmc0 = &sdmmc0; @@ -37,21 +33,20 @@ }; chosen: chosen { - power-key-factory-reset; - bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 rootpart=mmcblk1p3 rw rootwait autoresize=mmcblk1p4"; + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; }; adc_keys: adc-keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; + keyup-threshold-microvolt = <1750000>; poll-interval = <100>; vol-up-key { label = "volume up"; linux,code = ; - press-threshold-microvolt = <175000>; + press-threshold-microvolt = <1750>; }; vol-down-key { @@ -309,76 +304,6 @@ }; -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "input"; - - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - assigned-clock-rates = <0>, <125000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - phy-mode = "rgmii"; - clock_in_out = "input"; - - snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; - assigned-clock-rates = <0>, <125000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - - tx_delay = <0x4f>; - rx_delay = <0x26>; - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - realtek,led-data = <0xAC10>; - }; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - realtek,led-data = <0xAC10>; - }; -}; - &combphy0_us { rockchip,dis-u3otg0-port; /* disable USB3.0 */ status = "okay"; @@ -778,20 +703,6 @@ status = "okay"; }; -&nandc0 { - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - nand@0 { - reg = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <16>; - nand-ecc-step-size = <1024>; - }; -}; - &pinctrl { ir-receiver { ir_receiver_pin: ir-receiver-pin { @@ -1155,21 +1066,16 @@ status = "okay"; }; -/* fix mali warning */ -&gpu { - power-off-delay-ms = <200>; -}; - &pcie2x1 { reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; status = "okay"; - pcie@10 { - reg = <0x00100000 0 0 0 0>; + pcie@0,0 { + reg = <0x00000000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - pcie_eth0: pcie-eth@10,0 { + pcie_eth0: pcie@00,0 { compatible = "pci10ec,8125"; reg = <0x000000 0 0 0 0>; From fa3d7776524dcb6bf5ec96ea4c2d6418ad36b7f4 Mon Sep 17 00:00:00 2001 From: mingzq Date: Mon, 1 Jun 2026 07:14:23 +0000 Subject: [PATCH 19/32] net: r8169: add device tree based LED configuration for r8125 Read r8125 LED register/value pairs from the PCIe controller DT "realtek,led-data" property, instead of hardcoding in the shared driver path. Walk up the device parent chain to find the PCIe platform device's of_node, since PCI devices on Rockchip platforms do not have their of_node set directly. Parse the DT property once during probe and cache it in the driver private struct. Apply the cached config from rtl_hw_start_8125_common only, eliminating redundant calls and repeated memory allocation. --- .../rk3588-recomputer-rk3588-devkit.dts | 10 ++++ drivers/net/ethernet/realtek/r8169_main.c | 55 +++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts b/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts index 918c7c3430de1..90827ecf7ed62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-recomputer-rk3588-devkit.dts @@ -893,6 +893,11 @@ /* phy1 - right ethernet port PCIE20_1_TXP */ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + /* r8125 Ethernet LED configuration: + * LED0 (yellow): blink on traffic at all link speeds + * LED3 (green): solid on at all link speeds + */ + realtek,led-data = <0x18 0x022B 0x96 0x002B>; vpcie3v3-supply = <&vcc5v0_usb_eth>; status = "okay"; }; @@ -907,6 +912,11 @@ /* phy0 - left ethernet port PCIE20_0_TXP */ &pcie2x1l2 { reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + /* r8125 Ethernet LED configuration: + * LED0 (yellow): blink on traffic at all link speeds + * LED3 (green): solid on at all link speeds + */ + realtek,led-data = <0x18 0x022B 0x96 0x002B>; vpcie3v3-supply = <&vcc5v0_usb_eth>; status = "okay"; }; diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 75836c0e91cf3..0122ab05c82ee 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -659,6 +660,8 @@ struct rtl8169_private { struct rtl_fw *rtl_fw; u32 ocp_base; + u32 *led_data; + int led_data_count; }; typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); @@ -2564,6 +2567,53 @@ static void rtl_wol_enable_rx(struct rtl8169_private *tp) rtl_disable_rxdvgate(tp); } +/* Parse DT-based LED configuration for RTL8125, cache in tp. + * Walk up the device parent chain to find the PCIe platform + * device's of_node with the "realtek,led-data" property. + * Property format: realtek,led-data = ; + */ +static void rtl8125_parse_dt_led_config(struct rtl8169_private *tp) +{ + struct device_node *np = NULL; + struct device *d = &tp->pci_dev->dev; + int count; + + while (d && !np) { + np = d->of_node; + d = d->parent; + } + + if (!np) + return; + + count = of_property_count_u32_elems(np, "realtek,led-data"); + if (count < 2 || count % 2 != 0) + return; + + tp->led_data = kmalloc_array(count, sizeof(u32), GFP_KERNEL); + if (!tp->led_data) + return; + + if (of_property_read_u32_array(np, "realtek,led-data", tp->led_data, count)) { + kfree(tp->led_data); + tp->led_data = NULL; + return; + } + tp->led_data_count = count; +} + +/* Apply cached LED register/value pairs to hardware. */ +static void rtl8125_apply_dt_led_config(struct rtl8169_private *tp) +{ + int i; + + if (!tp->led_data) + return; + + for (i = 0; i < tp->led_data_count; i += 2) + RTL_W16(tp, tp->led_data[i], (u16)tp->led_data[i + 1]); +} + static void rtl_prepare_power_down(struct rtl8169_private *tp) { if (tp->dash_enabled) @@ -3690,6 +3740,7 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp) rtl8125a_config_eee_mac(tp); rtl_disable_rxdvgate(tp); + rtl8125_apply_dt_led_config(tp); } static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) @@ -5021,6 +5072,8 @@ static void rtl_remove_one(struct pci_dev *pdev) rtl_release_firmware(tp); + kfree(tp->led_data); + /* restore original MAC address */ rtl_rar_set(tp, tp->dev->perm_addr); } @@ -5488,6 +5541,8 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if (pci_dev_run_wake(pdev)) pm_runtime_put_sync(&pdev->dev); + rtl8125_parse_dt_led_config(tp); + return 0; } From 0ea24cc343399cf7513e29de863a6169a778b8c7 Mon Sep 17 00:00:00 2001 From: mingzhangqun Date: Mon, 1 Jun 2026 02:34:45 +0000 Subject: [PATCH 20/32] drm: rockchip: dw-dp: add AUX recovery and EDID cache for USB-C DP Alt Mode --- drivers/gpu/drm/rockchip/dw-dp.c | 51 ++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 2434cb49a0d39..d6cad517f4df8 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -507,6 +507,8 @@ struct dw_dp { struct list_head mst_conn_list; struct rockchip_dp_aux_client *aux_client; + struct edid *cached_edid; + struct drm_info_list *debugfs_files; struct typec_mux_dev *mux; }; @@ -1461,10 +1463,24 @@ static int dw_dp_connector_get_modes(struct drm_connector *connector) if (!num_modes) { edid = drm_bridge_get_edid(&dp->bridge, connector); if (edid) { + kfree(dp->cached_edid); + dp->cached_edid = kmemdup(edid, + (edid->extensions + 1) * EDID_LENGTH, + GFP_KERNEL); drm_connector_update_edid_property(connector, edid); num_modes = drm_add_edid_modes(connector, edid); dw_dp_update_hdr_property(connector); kfree(edid); + } else if (dp->cached_edid) { + dev_warn(dp->dev, "EDID read failed, using cached EDID\n"); + edid = kmemdup(dp->cached_edid, + (dp->cached_edid->extensions + 1) * EDID_LENGTH, + GFP_KERNEL); + if (edid) { + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } } } @@ -3121,6 +3137,7 @@ static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, unsigned long timeout = msecs_to_jiffies(10); u32 status, value; ssize_t ret = 0; + int retry; if (WARN_ON(msg->size > 16)) return -E2BIG; @@ -3150,11 +3167,37 @@ static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, value = FIELD_PREP(I2C_ADDR_ONLY, 1); value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); value |= FIELD_PREP(AUX_ADDR, msg->address); - regmap_write(dp->regmap, DPTX_AUX_CMD, value); + for (retry = 0; retry < 2; retry++) { + reinit_completion(&dp->complete); + regmap_write(dp->regmap, DPTX_AUX_CMD, value); + + status = wait_for_completion_timeout(&dp->complete, timeout); + if (status) + break; + + /* AUX timeout: reset AUX module and retry. On USB-C + * DP Alt Mode setups the AUX channel gets stuck after + * prolonged main link transmission. Reinitializing the + * completion and resetting the AUX module restores + * native AUX functionality for link training. + */ + if (retry == 0) { + dev_warn(dp->dev, "AUX timeout, resetting (cmd=0x%x addr=0x%x)\n", + msg->request, msg->address); + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, + AUX_RESET, AUX_RESET); + usleep_range(10, 20); + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, + AUX_RESET, 0); + usleep_range(100, 200); + dw_dp_aux_init(dp); + } + } - status = wait_for_completion_timeout(&dp->complete, timeout); if (!status) { - dev_dbg(dp->dev, "timeout waiting for AUX reply\n"); + regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); + dev_info(dp->dev, "AUX timeout after recovery: cmd=0x%x addr=0x%x size=%d, AUX_STATUS=0x%x\n", + msg->request, msg->address, msg->size, value); ret = -ETIMEDOUT; goto out; } @@ -4544,6 +4587,8 @@ static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge) return status; } if (status == connector_status_disconnected) { + kfree(dp->cached_edid); + dp->cached_edid = NULL; if (dp->is_mst) { dev_info(dp->dev, "MST device may have disappeared\n"); dp->is_mst = false; From d846f6af6f0bababdc7b572da52b69cd7c86bee4 Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Thu, 4 Jun 2026 17:57:07 +0800 Subject: [PATCH 21/32] arm64: dts: overlay: add radxa display 8hd for rock5t Signed-off-by: Ken Wang --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 + .../overlay/rock-5t-radxa-display-8hd.dts | 184 ++++++++++++++++++ 2 files changed, 185 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-radxa-display-8hd.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index c52c5080a0652..f0c96d1a86b52 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -58,6 +58,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ rock-5b-plus-cam0-radxa-camera-4k.dtbo \ rock-5b-plus-radxa-display-8hd.dtbo \ rock-5b-plus-radxa-display-10fhd.dtbo \ + rock-5t-radxa-display-8hd.dtbo \ rock-5t-radxa-display-10fhd.dtbo \ rock-5-itx-radxa-camera-4k-on-cam0.dtbo \ rock-5-itx-radxa-camera-4k-on-cam1.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-radxa-display-8hd.dts new file mode 100644 index 0000000000000..7bb5b81913d4d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-radxa-display-8hd.dts @@ -0,0 +1,184 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD"; + compatible = "radxa,rock-5t"; + category = "display"; + exclusive = "dsi1", "GPIO1_A2"; + description = "Enable Radxa Display 8HD."; + }; +}; + +&{/} { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 PWM_POLARITY_INVERTED>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; +}; + +&dsi1 { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; +}; + +&pinctrl { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; From ef081905db1f4dc39b5ddb465edb47889c2f5ffe Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Fri, 5 Jun 2026 15:57:23 +0800 Subject: [PATCH 22/32] arm64: dts: overlay: add some radxa devices overlay Signed-off-by: Ken Wang --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 34 +++ .../overlay/rock-5b-okdo-5mp-camera.dts | 176 +++++++++++++++ .../rock-5b-plus-cam0-okdo-5mp-camera.dts | 176 +++++++++++++++ ...rock-5b-plus-cam0-radxa-camera-13m-214.dts | 175 +++++++++++++++ .../rock-5b-plus-cam0-radxa-camera-8m-219.dts | 187 ++++++++++++++++ .../rock-5b-plus-cam0-rpi-camera-v1p3.dts | 176 +++++++++++++++ .../rock-5b-plus-cam0-rpi-camera-v2.dts | 9 + .../rock-5b-plus-cam1-okdo-5mp-camera.dts | 178 ++++++++++++++++ ...rock-5b-plus-cam1-radxa-camera-13m-214.dts | 177 ++++++++++++++++ .../rock-5b-plus-cam1-radxa-camera-4k.dts | 165 +++++++++++++++ .../rock-5b-plus-cam1-radxa-camera-8m-219.dts | 188 ++++++++++++++++ .../rock-5b-plus-cam1-rpi-camera-v1p3.dts | 178 ++++++++++++++++ .../rock-5b-plus-cam1-rpi-camera-v2.dts | 188 ++++++++++++++++ .../overlay/rock-5b-radxa-camera-13m-214.dts | 175 +++++++++++++++ .../overlay/rock-5b-radxa-camera-8m-219.dts | 186 ++++++++++++++++ .../overlay/rock-5b-rpi-camera-v1_3.dts | 176 +++++++++++++++ .../overlay/rock-5t-cam0-okdo-5mp-camera.dts | 178 ++++++++++++++++ .../rock-5t-cam0-radxa-camera-13m-214.dts | 175 +++++++++++++++ .../overlay/rock-5t-cam0-radxa-camera-4k.dts | 163 ++++++++++++++ .../rock-5t-cam0-radxa-camera-8m-219.dts | 187 ++++++++++++++++ .../overlay/rock-5t-cam0-rpi-camera-v1p3.dts | 15 ++ .../overlay/rock-5t-cam0-rpi-camera-v2.dts | 15 ++ .../overlay/rock-5t-cam1-okdo-5mp-camera.dts | 178 ++++++++++++++++ .../rock-5t-cam1-radxa-camera-13m-214.dts | 175 +++++++++++++++ .../overlay/rock-5t-cam1-radxa-camera-4k.dts | 165 +++++++++++++++ .../rock-5t-cam1-radxa-camera-8m-219.dts | 188 ++++++++++++++++ .../overlay/rock-5t-cam1-rpi-camera-v1p3.dts | 15 ++ .../overlay/rock-5t-cam1-rpi-camera-v2.dts | 15 ++ ...ock-5t-industrial-cam1-okdo-5mp-camera.dts | 175 +++++++++++++++ ...ock-5t-industrial-cam1-radxa-camera-4k.dts | 163 ++++++++++++++ ...5t-industrial-cam1-radxa-camera-8m-219.dts | 186 ++++++++++++++++ ...ock-5t-industrial-cam1-rpi-camera-v1p3.dts | 15 ++ .../rock-5t-industrial-cam1-rpi-camera-v2.dts | 15 ++ ...rock-5t-industrial-radxa-display-10fhd.dts | 200 ++++++++++++++++++ .../rock-5t-industrial-radxa-display-8hd.dts | 152 +++++++++++++ 35 files changed, 4919 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-13m-214.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-8m-219.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v1p3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-13m-214.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-4k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-8m-219.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v1p3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-13m-214.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-8m-219.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v1_3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-13m-214.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-4k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-8m-219.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v1p3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-13m-214.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-4k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-8m-219.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v1p3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-okdo-5mp-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-4k.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-8m-219.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v1p3.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-10fhd.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-8hd.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index f0c96d1a86b52..0a00b4b0f3075 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -48,18 +48,52 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ rock-5a-sata.dtbo \ rock-5b-hdmi1-8k.dtbo \ rock-5b-hdmi2-8k.dtbo \ + rock-5b-okdo-5mp-camera.dtbo \ rock-5b-pd-max-voltage-12v.dtbo \ rock-5b-radxa-display-10hd.dtbo \ rock-5b-radxa-display-8hd.dtbo \ rock-5b-radxa-display-10fhd.dtbo \ + rock-5b-rpi-camera-v1_3.dtbo \ rock-5b-rpi-camera-v2.dtbo \ + rock-5b-radxa-camera-13m-214.dtbo \ rock-5b-radxa-camera-4k.dtbo \ + rock-5b-radxa-camera-8m-219.dtbo \ rock-5b-sata.dtbo \ + rock-5b-plus-cam0-okdo-5mp-camera.dtbo \ + rock-5b-plus-cam0-rpi-camera-v1p3.dtbo \ + rock-5b-plus-cam0-rpi-camera-v2.dtbo \ + rock-5b-plus-cam0-radxa-camera-13m-214.dtbo \ rock-5b-plus-cam0-radxa-camera-4k.dtbo \ + rock-5b-plus-cam0-radxa-camera-8m-219.dtbo \ + rock-5b-plus-cam1-okdo-5mp-camera.dtbo \ + rock-5b-plus-cam1-radxa-camera-13m-214.dtbo \ + rock-5b-plus-cam1-radxa-camera-4k.dtbo \ + rock-5b-plus-cam1-radxa-camera-8m-219.dtbo \ + rock-5b-plus-cam1-rpi-camera-v1p3.dtbo \ + rock-5b-plus-cam1-rpi-camera-v2.dtbo \ rock-5b-plus-radxa-display-8hd.dtbo \ rock-5b-plus-radxa-display-10fhd.dtbo \ + rock-5t-cam0-okdo-5mp-camera.dtbo \ + rock-5t-cam0-rpi-camera-v1p3.dtbo \ + rock-5t-cam0-rpi-camera-v2.dtbo \ + rock-5t-cam0-radxa-camera-13m-214.dtbo \ + rock-5t-cam0-radxa-camera-4k.dtbo \ + rock-5t-cam0-radxa-camera-8m-219.dtbo \ + rock-5t-cam1-okdo-5mp-camera.dtbo \ + rock-5t-cam1-rpi-camera-v1p3.dtbo \ + rock-5t-cam1-rpi-camera-v2.dtbo \ + rock-5t-cam1-radxa-camera-13m-214.dtbo \ + rock-5t-cam1-radxa-camera-4k.dtbo \ + rock-5t-cam1-radxa-camera-8m-219.dtbo \ rock-5t-radxa-display-8hd.dtbo \ rock-5t-radxa-display-10fhd.dtbo \ + rock-5t-industrial-cam1-okdo-5mp-camera.dtbo \ + rock-5t-industrial-cam1-rpi-camera-v1p3.dtbo \ + rock-5t-industrial-cam1-rpi-camera-v2.dtbo \ + rock-5t-industrial-cam1-radxa-camera-4k.dtbo \ + rock-5t-industrial-cam1-radxa-camera-8m-219.dtbo \ + rock-5t-industrial-radxa-display-10fhd.dtbo \ + rock-5t-industrial-radxa-display-8hd.dtbo \ rock-5-itx-radxa-camera-4k-on-cam0.dtbo \ rock-5-itx-radxa-camera-4k-on-cam1.dtbo \ rock-5-itx-radxa-display-8hd-on-lcd0.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..697eaf68bd48a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-okdo-5mp-camera.dts @@ -0,0 +1,176 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera"; + compatible = "radxa,rock-5b"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable OKDO 5MP Camera."; + }; +}; + +&{/} { + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..c18f152d98661 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-okdo-5mp-camera.dts @@ -0,0 +1,176 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera on CAM0"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable OKDO 5MP Camera on CAM0."; + }; +}; + +&{/} { + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-13m-214.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-13m-214.dts new file mode 100644 index 0000000000000..be5dd699c58fe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-13m-214.dts @@ -0,0 +1,175 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 13M 214 on CAM0"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 13M 214 on CAM0."; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <3>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + }; + + imx214: imx214@10 { + status = "okay"; + compatible = "sony,imx214"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RADXA-CAMERA-13M"; + rockchip,camera-module-lens-name = "DEFAULT"; + lens-focus = <&dw9714>; + port { + imx214_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx214_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-8m-219.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-8m-219.dts new file mode 100644 index 0000000000000..3489980a81685 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-radxa-camera-8m-219.dts @@ -0,0 +1,187 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 8M 219 on CAM0"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 8M 219 on CAM0."; + }; +}; + +&{/} { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-8M"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v1p3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v1p3.dts new file mode 100644 index 0000000000000..b5866b41f3589 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v1p3.dts @@ -0,0 +1,176 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera v1.3 on CAM0"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera v1.3 on CAM0."; + }; +}; + +&{/} { + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v1p3"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v2.dts new file mode 100644 index 0000000000000..90d97e8a7383a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam0-rpi-camera-v2.dts @@ -0,0 +1,9 @@ +#include "rock-5b-rpi-camera-v2.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2 on CAM0"; + compatible = "radxa,rock-5b-plus"; + description = "Enable Raspberry Pi Camera V2 on CAM0."; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..ab133fb712a84 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-okdo-5mp-camera.dts @@ -0,0 +1,178 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera on CAM1"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy4"; + description = "Enable OKDO 5MP Camera on CAM1."; + }; +}; + +&{/} { + clk_cam_25m_1: external-camera-clock-25m-1 { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m_1"; + #clock-cells = <0>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m_1>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk_1"; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-13m-214.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-13m-214.dts new file mode 100644 index 0000000000000..efb3f93d3404f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-13m-214.dts @@ -0,0 +1,177 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 13M 214 on CAM1"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy1"; + description = "Enable Radxa Camera 13M 214 on CAM1."; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dw9714_1: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <3>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx214_1: imx214-1@10 { + status = "okay"; + compatible = "sony,imx214"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + lens-focus = <&dw9714_1>; + port { + imx214_1_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx214_1_out4>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-4k.dts new file mode 100644 index 0000000000000..47715ca209f6e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-4k.dts @@ -0,0 +1,165 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM1"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy1"; + description = "Enable Radxa Camera 4K on CAM1."; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out4>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-8m-219.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-8m-219.dts new file mode 100644 index 0000000000000..330d1584b66cd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-radxa-camera-8m-219.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 8M 219 on CAM1"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy4"; + description = "Enable Radxa Camera 8M 219 on CAM1."; + }; +}; + +&{/} { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m_1: external-camera-clock-24m-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m_1"; + #clock-cells = <0>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m_1>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-8M"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v1p3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v1p3.dts new file mode 100644 index 0000000000000..af8c61cd09203 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v1p3.dts @@ -0,0 +1,178 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera v1.3 on CAM1"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy4"; + description = "Enable Raspberry Pi Camera v1.3 on CAM1."; + }; +}; + +&{/} { + clk_cam_25m_1: external-camera-clock-25m-1 { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m_1"; + #clock-cells = <0>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m_1>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk_1"; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v1p3"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v2.dts new file mode 100644 index 0000000000000..15caf10ffe23d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-plus-cam1-rpi-camera-v2.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2 on CAM1"; + compatible = "radxa,rock-5b-plus"; + category = "camera"; + exclusive = "csi2_dphy4"; + description = "Enable Raspberry Pi Camera V2 on CAM1."; + }; +}; + +&{/} { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m_1: external-camera-clock-24m-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m_1"; + #clock-cells = <0>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m_1>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-13m-214.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-13m-214.dts new file mode 100644 index 0000000000000..169a5fdf45f26 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-13m-214.dts @@ -0,0 +1,175 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 13M 214"; + compatible = "radxa,rock-5b"; + category = "camera"; + exclusive = "GPIO1_B0", "GPIO4_A0", "csi2_dphy0", "i2c3"; + description = "Enable Radxa Camera 13M 214."; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <3>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx214: imx214@10 { + status = "okay"; + compatible = "sony,imx214"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-13M"; + rockchip,camera-module-lens-name = "DEFAULT"; + lens-focus = <&dw9714>; + port { + imx214_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx214_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-8m-219.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-8m-219.dts new file mode 100644 index 0000000000000..65d778b0c0297 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-radxa-camera-8m-219.dts @@ -0,0 +1,186 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 8M 219"; + compatible = "radxa,rock-5b"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 8M 219."; + }; +}; + +&{/} { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-8M"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v1_3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v1_3.dts new file mode 100644 index 0000000000000..362e3d2f17649 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5b-rpi-camera-v1_3.dts @@ -0,0 +1,176 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Raspberry Pi Camera v1.3"; + compatible = "radxa,rock-5b"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Raspberry Pi Camera v1.3."; + }; +}; + +&{/} { + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v1p3"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..8e6f865992282 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-okdo-5mp-camera.dts @@ -0,0 +1,178 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera on CAM0"; + compatible = "radxa,rock-5t", "radxa,rock-5t-industrial"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable OKDO 5MP Camera on CAM0."; + }; +}; + +&{/} { + clk_cam_25m: external-camera-clock-25m { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m>; + pwdn-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-13m-214.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-13m-214.dts new file mode 100644 index 0000000000000..c22309b87a9b3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-13m-214.dts @@ -0,0 +1,175 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 13M 214 on CAM0"; + compatible = "radxa,rock-5t"; + category = "camera"; + exclusive = "GPIO1_D3", "GPIO2_C5", "csi2_dphy0", "i2c3"; + description = "Enable Radxa Camera 13M 214 on CAM0."; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <3>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx214: imx214@10 { + status = "okay"; + compatible = "sony,imx214"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-13M"; + rockchip,camera-module-lens-name = "DEFAULT"; + lens-focus = <&dw9714>; + port { + imx214_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx214_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-4k.dts new file mode 100644 index 0000000000000..54ce3d9126c6e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-4k.dts @@ -0,0 +1,163 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM0"; + compatible = "radxa,rock-5t", "radxa,rock-5t-industrial"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 4K on CAM0."; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-8m-219.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-8m-219.dts new file mode 100644 index 0000000000000..2aba04940b74e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-radxa-camera-8m-219.dts @@ -0,0 +1,187 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 8M 219 on CAM0"; + compatible = "radxa,rock-5t", "radxa,rock-5t-industrial"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable Radxa Camera 8M 219 on CAM0."; + }; +}; + +&{/} { + camera_pwdn_gpio: camera-pwdn-gpio { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio>; + }; + + clk_cam_24m: external-camera-clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m"; + #clock-cells = <0>; + }; +}; + +&i2c3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219: camera-imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-8M"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v1p3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v1p3.dts new file mode 100644 index 0000000000000..6cede081b971f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v1p3.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "rock-5t-cam0-okdo-5mp-camera.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera v1.3 on CAM0"; + description = "Enable Raspberry Pi Camera v1.3 on CAM0."; + }; +}; + +&ov5647{ + rockchip,camera-module-name = "rpi-camera-v1p3"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v2.dts new file mode 100644 index 0000000000000..7b6e5c66b13a9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam0-rpi-camera-v2.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "rock-5t-cam0-radxa-camera-8m-219.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera V2 on CAM0"; + description = "Enable Raspberry Pi Camera V2 on CAM0."; + }; +}; + +&camera_imx219 { + rockchip,camera-module-name = "rpi-camera-v2"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..6a2d70663b4b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-okdo-5mp-camera.dts @@ -0,0 +1,178 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera on CAM1"; + compatible = "radxa,rock-5t"; + category = "camera"; + exclusive = "csi2_dphy1"; + description = "Enable OKDO 5MP Camera on CAM1."; + }; +}; + +&{/} { + clk_cam_25m_1: external-camera-clock-25m-1 { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m_1"; + #clock-cells = <0>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m_1>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk_1"; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-13m-214.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-13m-214.dts new file mode 100644 index 0000000000000..db12e70c02d26 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-13m-214.dts @@ -0,0 +1,175 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 13M 214 on CAM1"; + compatible = "radxa,rock-5t"; + category = "camera"; + exclusive = "GPIO2_A6", "GPIO2_B0", "csi2_dphy1", "i2c4"; + description = "Enable Radxa Camera 13M 214 on CAM1."; + }; +}; + +&i2c4 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dw9714_1: dw9714-1@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <3>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + imx214_1: imx214-1@10 { + status = "okay"; + compatible = "sony,imx214"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-13M"; + rockchip,camera-module-lens-name = "DEFAULT"; + lens-focus = <&dw9714_1>; + port { + imx214_1_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx214_1_out4>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-4k.dts new file mode 100644 index 0000000000000..f1e2ee8904f61 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-4k.dts @@ -0,0 +1,165 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM1"; + compatible = "radxa,rock-5t"; + category = "camera"; + exclusive = "csi2_dphy1"; + description = "Enable Radxa Camera 4K on CAM1."; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out4>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-8m-219.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-8m-219.dts new file mode 100644 index 0000000000000..42f835e4b04df --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-radxa-camera-8m-219.dts @@ -0,0 +1,188 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 8M 219 on CAM1"; + compatible = "radxa,rock-5t"; + category = "camera"; + exclusive = "csi2_dphy4"; + description = "Enable Radxa Camera 8M 219 on CAM1."; + }; +}; + +&{/} { + camera_pwdn_gpio_1: camera-pwdn-gpio-1 { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio_1"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio_1>; + }; + + clk_cam_24m_1: external-camera-clock-24m-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m_1"; + #clock-cells = <0>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219_1: camera-imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m_1>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-8M"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio_1: cam-pwdn-gpio-1 { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v1p3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v1p3.dts new file mode 100644 index 0000000000000..349a994d0b704 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v1p3.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "rock-5t-cam1-okdo-5mp-camera.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera v1.3 on CAM1"; + description = "Enable Raspberry Pi Camera v1.3 on CAM1."; + }; +}; + +&ov5647 { + rockchip,camera-module-name = "rpi-camera-v1p3"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v2.dts new file mode 100644 index 0000000000000..7c8d2fd38036e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-cam1-rpi-camera-v2.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "rock-5t-cam1-radxa-camera-8m-219.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera v2 on CAM1"; + description = "Enable Raspberry Pi Camera v2 on CAM1."; + }; +}; + +&camera_imx219_1 { + rockchip,camera-module-name = "rpi-camera-v2"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-okdo-5mp-camera.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-okdo-5mp-camera.dts new file mode 100644 index 0000000000000..d80786ca0db88 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-okdo-5mp-camera.dts @@ -0,0 +1,175 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable OKDO 5MP Camera on CAM1"; + compatible = "radxa,rock-5t-industrial"; + category = "camera"; + exclusive = "csi2_dphy1"; + description = "Enable OKDO 5MP Camera on CAM1."; + }; +}; + +&{/} { + clk_cam_25m_1: external-camera-clock-25m-1 { + status = "okay"; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "clk_cam_25m_1"; + #clock-cells = <0>; + }; +}; +&i2c6 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ov5647: ov5647@36 { + status = "okay"; + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&clk_cam_25m_1>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + clock-names = "ext_cam_clk_1"; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "OKDO-5MP"; + rockchip,camera-module-lens-name = "default"; + + port { + ov5647_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5647_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio: cam-pwdn-gpio { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-4k.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-4k.dts new file mode 100644 index 0000000000000..ad14306b7e2d9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-4k.dts @@ -0,0 +1,163 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 4K on CAM1"; + compatible = "radxa,rock-5t-industrial"; + category = "camera"; + exclusive = "csi2_dphy1"; + description = "Enable Radxa Camera 4K on CAM1."; + }; +}; + +&i2c6 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + status = "okay"; + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-4K"; + rockchip,camera-module-lens-name = "DEFAULT"; + port { + imx415_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out4>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-8m-219.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-8m-219.dts new file mode 100644 index 0000000000000..ebd669f91bc6e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-radxa-camera-8m-219.dts @@ -0,0 +1,186 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title ="Enable Radxa Camera 8M 219 on CAM1"; + compatible = "radxa,rock-5t-industrial"; + category = "camera"; + exclusive = "csi2_dphy4"; + description = "Enable Radxa Camera 8M 219 on CAM1."; + }; +}; + +&{/} { + camera_pwdn_gpio_1: camera-pwdn-gpio-1 { + compatible = "regulator-fixed"; + regulator-name = "camera_pwdn_gpio_1"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwdn_gpio_1>; + }; + + clk_cam_24m_1: external-camera-clock-24m-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "clk_cam_24m_1"; + #clock-cells = <0>; + }; +}; + +&i2c6 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + camera_imx219_1: camera-imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_24m_1>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RADXA-CAMERA-8M"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out4: endpoint { + remote-endpoint = <&mipidphy4_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy4_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&imx219_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi4_in0: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi_lvds4_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds4_sditf>; + }; + }; +}; + +&pinctrl { + camera { + cam_pwdn_gpio_1: cam-pwdn-gpio-1 { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v1p3.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v1p3.dts new file mode 100644 index 0000000000000..cb44256985b77 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v1p3.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "rock-5t-industrial-cam1-okdo-5mp-camera.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera v1.3 on CAM1"; + description = "Enable Raspberry Pi Camera v1.3 on CAM1."; + }; +}; + +&ov5647 { + rockchip,camera-module-name = "rpi-camera-v1p3"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v2.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v2.dts new file mode 100644 index 0000000000000..15fd38bb01f65 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-cam1-rpi-camera-v2.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include "rock-5t-industrial-cam1-radxa-camera-8m-219.dts" + +/ { + metadata { + title ="Enable Raspberry Pi Camera v2 on CAM1"; + description = "Enable Raspberry Pi Camera v2 on CAM1."; + }; +}; + +&camera_imx219_1 { + rockchip,camera-module-name = "rpi-camera-v2"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-10fhd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-10fhd.dts new file mode 100644 index 0000000000000..3c5857a527077 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-10fhd.dts @@ -0,0 +1,200 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 10FHD"; + compatible = "radxa,rock-5t-industrial"; + category = "display"; + exclusive = "dsi1", "GPIO1_A2"; + description = "Enable Radxa Display 10FHD."; + }; +}; + +&{/} { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; +}; + +&pwm4 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m1_pins>; +}; + +&dsi1{ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + prepare-delay-ms = <120>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + enable-delay-ms = <100>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + + width-mm = <62>; + height-mm = <110>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + + vback-porch = <25>; + vfront-porch = <35>; + + hback-porch = <60>; + hfront-porch = <80>; + + hsync-len = <4>; + vsync-len = <4>; + + vsync-active = <0>; + hsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <9271>; + tp-supply = <&vcc_lcd_mipi1>; + }; +}; + +&pinctrl { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-8hd.dts new file mode 100644 index 0000000000000..460c1355c1e23 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rock-5t-industrial-radxa-display-8hd.dts @@ -0,0 +1,152 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title ="Enable Radxa Display 8HD"; + compatible = "radxa,rock-5t-industrial"; + category = "display"; + exclusive = "dsi1", "GPIO1_A2"; + description = "Enable Radxa Display 8HD."; + }; +}; + +&{/} { + vcc_lcd_mipi1: vcc-lcd-mipi1 { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi1"; + gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dsi1_backlight: dsi1-backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <200>; + enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + }; +}; + +&pwm4 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m1_pins>; +}; + +&dsi1 { + status = "okay"; + rockchip,lane-rate = <480>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "radxa,display-8hd"; + reg = <0>; + backlight = <&dsi1_backlight>; + + vdd-supply = <&vcc_lcd_mipi1>; + vccio-supply = <&vcc_1v8_s0>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_mipi1>; + }; +}; + +&pinctrl { + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; From 64a81719293a34ef3a116a1d71350bea4c2e749a Mon Sep 17 00:00:00 2001 From: SuperKali Date: Wed, 10 Jun 2026 12:59:48 +0200 Subject: [PATCH 23/32] arm64: dts: rockchip: yy3588: bind ES8388 codec via es8328 driver (#499) --- .../boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts index 4542594f44ae9..8baca5dceb975 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts @@ -84,8 +84,8 @@ status = "okay"; }; - /* AUDIO - ES8388 chip, but only works with ES8323 driver */ - es8323_sound: es8323-sound { + /* AUDIO - ES8388 */ + es8388_sound: analog-sound { compatible = "rockchip,multicodecs-card"; hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; io-channel-names = "adc-detect"; @@ -107,8 +107,8 @@ "LINPUT2", "Main Mic", "RINPUT1", "Headset Mic", "RINPUT2", "Headset Mic"; - rockchip,card-name = "rockchip-es8323"; - rockchip,codec = <&es8323>; + rockchip,card-name = "rockchip-es8388"; + rockchip,codec = <&es8388>; rockchip,cpu = <&i2s0_8ch>; rockchip,format = "i2s"; rockchip,mclk-fs = <256>; @@ -605,9 +605,9 @@ &i2c7 { status = "okay"; - /* Audio codec: ES8388 chip, but only works with ES8323 driver */ - es8323: es8323@11 { - compatible = "everest,es8323"; + /* Audio codec: ES8388 */ + es8388: es8388@11 { + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; #sound-dai-cells = <0>; assigned-clock-rates = <12288000>; From 95e85f6cb496c75807c5b16f158853578e7e7d1b Mon Sep 17 00:00:00 2001 From: Mecid Date: Sun, 14 Jun 2026 19:47:08 +0200 Subject: [PATCH 24/32] ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585 (#504) --- drivers/ata/ahci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 20f53ae4d204e..53010a97fed78 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -61,6 +61,7 @@ enum board_ids { /* board IDs for specific chipsets in alphabetical order */ board_ahci_al, board_ahci_avn, + board_ahci_jmb585, board_ahci_mcp65, board_ahci_mcp77, board_ahci_mcp89, @@ -200,6 +201,15 @@ static const struct ata_port_info ahci_port_info[] = { .udma_mask = ATA_UDMA6, .port_ops = &ahci_avn_ops, }, + /* JMicron JMB582/585: 64-bit DMA is broken, force 32-bit */ + [board_ahci_jmb585] = { + AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR | + AHCI_HFLAG_32BIT_ONLY), + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, + }, [board_ahci_mcp65] = { AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ), @@ -433,6 +443,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ + /* JMicron JMB582/585: force 32-bit DMA (broken 64-bit implementation) */ + { PCI_VDEVICE(JMICRON, 0x0582), board_ahci_jmb585 }, + { PCI_VDEVICE(JMICRON, 0x0585), board_ahci_jmb585 }, /* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, From e45d4e0df629fbed3744a499f8acb01bbd7760de Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sat, 4 Jul 2026 23:01:52 +0200 Subject: [PATCH 25/32] input: gt9xx: add TPC2059 and GT928 vendor touch configs The 7" 1024x600 DSI kit on Youyeetoo R1 and YY3588 is a TPC2059 panel whose GT911 needs the vendor cfg blob, and the 11.6" eDP kit ships a GT928 wired portrait. Add both blobs from the youyeetoo yy3588_linux tree as new tp-size cases 2059 and 928 so existing boards keep their current behavior. Signed-off-by: SuperKali --- .../touchscreen/gt9xx/2059-V1-1024X600.cfg | 1 + .../gt9xx/GT928_Config_20190318_111541.cfg | 1 + .../TPC2059-7.0-Config_20241122_143209.cfg | 1 + drivers/input/touchscreen/gt9xx/gt9xx.c | 30 +++++++++++++++++++ drivers/input/touchscreen/gt9xx/gt9xx_cfg.h | 10 +++++++ 5 files changed, 43 insertions(+) create mode 100755 drivers/input/touchscreen/gt9xx/2059-V1-1024X600.cfg create mode 100755 drivers/input/touchscreen/gt9xx/GT928_Config_20190318_111541.cfg create mode 100755 drivers/input/touchscreen/gt9xx/TPC2059-7.0-Config_20241122_143209.cfg diff --git a/drivers/input/touchscreen/gt9xx/2059-V1-1024X600.cfg b/drivers/input/touchscreen/gt9xx/2059-V1-1024X600.cfg new file mode 100755 index 0000000000000..9a326dad6b76f --- /dev/null +++ b/drivers/input/touchscreen/gt9xx/2059-V1-1024X600.cfg @@ -0,0 +1 @@ +0x50,0x00,0x04,0x58,0x02,0x05,0x0D,0x00,0x01,0x0A,0x28,0x0F,0x50,0x32,0x03,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x17,0x19,0x1C,0x14,0x8C,0x2D,0x0E,0x4E,0x50,0xEB,0x04,0x00,0x00,0x00,0x00,0x02,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x46,0x64,0x94,0xC5,0x02,0x07,0x00,0x00,0x04,0x9E,0x48,0x00,0x8D,0x4D,0x00,0x7F,0x53,0x00,0x73,0x59,0x00,0x67,0x60,0x00,0x67,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x04,0x06,0x08,0x0A,0x0C,0x0E,0x10,0x12,0x14,0x16,0x18,0x1A,0x1C,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x02,0x04,0x06,0x08,0x0A,0x0C,0x0F,0x10,0x12,0x13,0x14,0x18,0x1C,0x1D,0x1E,0x1F,0x20,0x21,0x22,0x24,0x26,0x28,0x29,0x2A,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x20,0x01 \ No newline at end of file diff --git a/drivers/input/touchscreen/gt9xx/GT928_Config_20190318_111541.cfg b/drivers/input/touchscreen/gt9xx/GT928_Config_20190318_111541.cfg new file mode 100755 index 0000000000000..6ca7b76802101 --- /dev/null +++ b/drivers/input/touchscreen/gt9xx/GT928_Config_20190318_111541.cfg @@ -0,0 +1 @@ +0x45,0x80,0x07,0x38,0x04,0x0A,0x35,0x00,0x01,0x08,0x28,0x0F,0x5A,0x46,0x03,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1A,0x1C,0x1E,0x14,0x90,0x30,0xCC,0x1F,0x21,0x7C,0x06,0x00,0x00,0x02,0x21,0x03,0x2D,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x32,0x94,0xC5,0x02,0x07,0x00,0x00,0x04,0xA9,0x16,0x00,0x93,0x1A,0x00,0x7F,0x1F,0x00,0x6D,0x26,0x00,0x61,0x2D,0x00,0x61,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1D,0x1C,0x1B,0x1A,0x19,0x18,0x17,0x16,0x15,0x14,0x11,0x10,0x0F,0x0E,0x0D,0x0C,0x09,0x08,0x07,0x06,0x05,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2A,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x20,0x1F,0x1E,0x1C,0x1B,0x19,0x14,0x13,0x12,0x11,0x10,0x0F,0x0E,0x0D,0x0C,0x0A,0x08,0x07,0x06,0x04,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x01 \ No newline at end of file diff --git a/drivers/input/touchscreen/gt9xx/TPC2059-7.0-Config_20241122_143209.cfg b/drivers/input/touchscreen/gt9xx/TPC2059-7.0-Config_20241122_143209.cfg new file mode 100755 index 0000000000000..2f3cf51816cc2 --- /dev/null +++ b/drivers/input/touchscreen/gt9xx/TPC2059-7.0-Config_20241122_143209.cfg @@ -0,0 +1 @@ +0x50,0x00,0x04,0x58,0x02,0x05,0x0D,0x00,0x01,0x0A,0x28,0x0F,0x50,0x32,0x03,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x17,0x19,0x1C,0x14,0x87,0x29,0x0A,0x4E,0x50,0xEB,0x04,0x00,0x00,0x00,0x00,0x02,0x11,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x46,0x64,0x94,0xC5,0x02,0x07,0x00,0x00,0x04,0x9E,0x48,0x00,0x8D,0x4D,0x00,0x7F,0x53,0x00,0x73,0x59,0x00,0x67,0x60,0x00,0x67,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x04,0x06,0x08,0x0A,0x0C,0x0E,0x10,0x12,0x14,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x04,0x06,0x08,0x0A,0x0C,0x1D,0x1E,0x1F,0x20,0x21,0x22,0x24,0x26,0x28,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x5C,0x01 \ No newline at end of file diff --git a/drivers/input/touchscreen/gt9xx/gt9xx.c b/drivers/input/touchscreen/gt9xx/gt9xx.c index b1a49235b102f..71c0d8bbdd0ac 100644 --- a/drivers/input/touchscreen/gt9xx/gt9xx.c +++ b/drivers/input/touchscreen/gt9xx/gt9xx.c @@ -63,6 +63,8 @@ static u8 bgt9110 = FALSE; static u8 bgt9111 = FALSE; static u8 bgt970 = FALSE; static u8 bgt910 = FALSE; +static u8 bgt2059 = FALSE; +static u8 bgt928 = FALSE; static u8 gtp_change_x2y = TRUE; static u8 gtp_x_reverse = FALSE; static u8 gtp_y_reverse = TRUE; @@ -1478,6 +1480,16 @@ static s32 gtp_init_panel(struct goodix_ts_data *ts) cfg_info_len[0] = CFG_GROUP_LEN(gtp_dat_7); } + if (bgt2059) { + send_cfg_buf[0] = gtp_dat_tpc2059; + cfg_info_len[0] = CFG_GROUP_LEN(gtp_dat_tpc2059); + } + + if (bgt928) { + send_cfg_buf[0] = gtp_dat_gt928; + cfg_info_len[0] = CFG_GROUP_LEN(gtp_dat_gt928); + } + GTP_DEBUG_FUNC(); GTP_DEBUG("Config Groups\' Lengths: %d, %d, %d, %d, %d, %d", cfg_info_len[0], cfg_info_len[1], cfg_info_len[2], cfg_info_len[3], @@ -2696,6 +2708,24 @@ static int goodix_ts_probe(struct i2c_client *client, const struct i2c_device_id gtp_change_x2y = TRUE; gtp_x_reverse = FALSE; gtp_y_reverse = FALSE; + } else if (val == 2059) { + /* TPC2059 7" 1024x600 panel (Youyeetoo R1 / YY3588 DSI kits): + * vendor cfg blob reports raw coordinates 1:1 with the panel. + */ + m89or101 = FALSE; + bgt2059 = TRUE; + gtp_change_x2y = FALSE; + gtp_x_reverse = FALSE; + gtp_y_reverse = FALSE; + } else if (val == 928) { + /* GT928 11.6" 1920x1080 eDP kit (Youyeetoo YY3588): sensor is + * portrait-wired, swap axes and reverse X per vendor tuning. + */ + m89or101 = FALSE; + bgt928 = TRUE; + gtp_change_x2y = TRUE; + gtp_x_reverse = TRUE; + gtp_y_reverse = FALSE; } else if (val == 970) { m89or101 = FALSE; bgt911 = FALSE; diff --git a/drivers/input/touchscreen/gt9xx/gt9xx_cfg.h b/drivers/input/touchscreen/gt9xx/gt9xx_cfg.h index 715911554c021..78f273c5e0efc 100644 --- a/drivers/input/touchscreen/gt9xx/gt9xx_cfg.h +++ b/drivers/input/touchscreen/gt9xx/gt9xx_cfg.h @@ -67,4 +67,14 @@ static u8 gtp_dat_7[] = { #include "WGJ10187_GT910_Config_20140623_104014_0X41.cfg" }; +static u8 gtp_dat_tpc2059[] = { + /* <1024, 600> TPC2059 7.0 (Youyeetoo R1 / YY3588 DSI kit) */ + #include "TPC2059-7.0-Config_20241122_143209.cfg" +}; + +static u8 gtp_dat_gt928[] = { + /* <1920, 1080> 11.6 eDP (Youyeetoo YY3588 eDP kit) */ + #include "GT928_Config_20190318_111541.cfg" +}; + #endif /* _GOODIX_GT9XX_CFG_H_ */ From e9110027be1bde70404a593ad5be211d243441d4 Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sat, 4 Jul 2026 23:02:12 +0200 Subject: [PATCH 26/32] arm64: dts: rockchip: yy3588: move hdmirx-det to GPIO1_D5 Vendor evb7-v11 wires HDMI-RX hotplug detect on GPIO1_D5, not GPIO1_C6. GPIO1_C6 is the pwm15m2 pad used by the eDP kit backlight, so keeping detect there breaks the eDP overlay pinmux. Signed-off-by: SuperKali --- arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts index 8baca5dceb975..4338f6f3f948b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts @@ -442,7 +442,7 @@ /* Should work with at least 256MB cma reserved above. */ &hdmirx_ctrler { #sound-dai-cells = <1>; - hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; hpd-trigger-level = <1>; pinctrl-names = "default"; pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; @@ -745,7 +745,7 @@ &pinctrl { hdmi { hdmirx_det: hdmirx-det { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; From 4ade28c98dab8dfa6bed3f734a019cc9488b7907 Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sat, 4 Jul 2026 23:02:12 +0200 Subject: [PATCH 27/32] arm64: dts: rockchip: overlay: youyeetoo-r1: use TPC2059 touch config tp-size 911 programs the WGJ89006B 4096x4096 blob, which does not match the 7" TPC2059 sensor matrix and leaves dead zones at the panel edges. Switch both DSI overlays to the new 2059 case that sends the vendor 1024x600 blob with 1:1 coordinates. Signed-off-by: SuperKali --- .../boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts | 2 +- .../boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts index 56d2a063584b3..ec3e07d63a03e 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts @@ -204,7 +204,7 @@ reset-gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; max-x = <1024>; max-y = <600>; - tp-size = <911>; + tp-size = <2059>; pinctrl-names = "default"; pinctrl-0 = <&touch_gpio>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts index 0a8b0019ab606..63b34e06daed9 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts @@ -203,7 +203,7 @@ reset-gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; max-x = <1024>; max-y = <600>; - tp-size = <911>; + tp-size = <2059>; pinctrl-names = "default"; pinctrl-0 = <&touch_gpio>; status = "okay"; From ecf96e554678a31578370b5b86c3bc6ed90ce5a5 Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sat, 4 Jul 2026 23:02:13 +0200 Subject: [PATCH 28/32] arm64: dts: rockchip: overlay: yy3588: add dsi0/dsi1/edp display overlays Wire the three official Youyeetoo display kits from the vendor rk3588-lcd-yyt.dtsi: 7" 1024x600 TPC2059 panels on dsi0 and dsi1 and the 11.6" 1920x1080 eDP panel with GT928 touch. The previous dsi1 overlay described a non-existent Innolux panel. eDP runs on VP1 because dp0 already owns VP2 on this board. Signed-off-by: SuperKali --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 2 + .../overlay/youyeetoo-yy3588-display-dsi0.dts | 254 ++++++++++++++++++ .../overlay/youyeetoo-yy3588-display-dsi1.dts | 168 +++++++++--- .../overlay/youyeetoo-yy3588-display-edp.dts | 224 +++++++++++++++ 4 files changed, 604 insertions(+), 44 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index 0a00b4b0f3075..d4b3f58d7e704 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -124,7 +124,9 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ youyeetoo-r1-display-dsi1.dtbo \ youyeetoo-yy3588-camera0-gc8034.dtbo \ youyeetoo-yy3588-camera1-gc8034.dtbo \ + youyeetoo-yy3588-display-dsi0.dtbo \ youyeetoo-yy3588-display-dsi1.dtbo \ + youyeetoo-yy3588-display-edp.dtbo \ khadas-edge2-display-dsi0.dtbo \ khadas-edge2-display-dsi1.dtbo \ khadas-edge2-cam1.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts new file mode 100644 index 0000000000000..5586bb7f20575 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts @@ -0,0 +1,254 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/* + * Youyeetoo YY3588 - RK3588 + * 7" 1024x600 LCD on DSI0 (TPC2059 panel, GT911 touch) + */ + +/ { + metadata { + title = "Enable DSI0 Display on Youyeetoo YY3588"; + compatible = "youyeetoo,yy3588"; + category = "display"; + description = "Enable 7 inch 1024x600 MIPI DSI0 display with GT911 touchscreen"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_dsi0: backlight-dsi0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm1 0 25000 0>; + power-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; + }; + }; + + fragment@1 { + target = <&pwm1>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + }; + }; + + fragment@2 { + target = <&dsi0>; + + __overlay__ { + status = "okay"; + rockchip,lane-rate = <1000>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight_dsi0>; + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_dsi0_rst_gpio>; + + panel-init-sequence = [ + 15 00 02 80 ac + 15 00 02 81 b8 + 15 00 02 82 09 + 15 00 02 83 78 + 15 00 02 84 7f + 15 00 02 85 bb + 15 00 02 86 70 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <51668640>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hback-porch = <160>; + hsync-len = <10>; + vfront-porch = <12>; + vsync-len = <10>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&route_dsi0>; + + __overlay__ { + status = "okay"; + connect = <&vp3_out_dsi0>; + }; + }; + + fragment@4 { + target = <&dsi0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&dsi0_in_vp3>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&mipi_dcphy0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c5>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx_dsi0: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + max-x = <1024>; + max-y = <600>; + tp-size = <2059>; + tp-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_dsi0_gpio>; + status = "okay"; + }; + }; + }; + + fragment@8 { + target = <&pinctrl>; + + __overlay__ { + lcd { + lcd_dsi0_rst_gpio: lcd-dsi0-rst-gpio { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_dsi0_gpio: touch-dsi0-gpio { + rockchip,pins = + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts index 9c00eb5dfaa3e..77f3f1cc29943 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts @@ -2,38 +2,42 @@ /plugin/; #include -#include #include +#include + +/* + * Youyeetoo YY3588 - RK3588 + * 7" 1024x600 LCD on DSI1 (TPC2059 panel, GT911 touch) + */ / { metadata { title = "Enable DSI1 Display on Youyeetoo YY3588"; compatible = "youyeetoo,yy3588"; category = "display"; - description = "Enable MIPI DSI1 display with Goodix GT9271 touchscreen"; + description = "Enable 7 inch 1024x600 MIPI DSI1 display with GT911 touchscreen"; }; fragment@0 { target-path = "/"; __overlay__ { - backlight: backlight { + backlight_dsi1: backlight-dsi1 { compatible = "pwm-backlight"; - pwms = <&pwm2 0 25000 0>; brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 @@ -55,16 +59,29 @@ 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + power-supply = <&vcc5v0_sys>; status = "okay"; }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; }; }; fragment@1 { - target = <&mipi_dcphy1>; + target = <&pwm0>; __overlay__ { status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; }; }; @@ -73,18 +90,61 @@ __overlay__ { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_te1>; + rockchip,lane-rate = <1000>; dsi1_panel: panel@0 { status = "okay"; - compatible = "innolux,afj101-ba2131"; + compatible = "simple-panel-dsi"; reg = <0>; - backlight = <&backlight>; - reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_dsi1>; + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; + pinctrl-0 = <&lcd_dsi1_rst_gpio>; + + panel-init-sequence = [ + 15 00 02 80 ac + 15 00 02 81 b8 + 15 00 02 82 09 + 15 00 02 83 78 + 15 00 02 84 7f + 15 00 02 85 bb + 15 00 02 86 70 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <51668640>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hback-porch = <160>; + hsync-len = <10>; + vfront-porch = <12>; + vsync-len = <10>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; ports { #address-cells = <1>; @@ -114,57 +174,77 @@ }; fragment@3 { - target = <&dsi1_in_vp2>; + target = <&route_dsi1>; __overlay__ { - status = "disabled"; + status = "okay"; + connect = <&vp3_out_dsi1>; }; }; fragment@4 { - target = <&dsi1_in_vp3>; + target = <&dsi1_in_vp2>; __overlay__ { - status = "okay"; + status = "disabled"; }; }; fragment@5 { - target = <&route_dsi1>; + target = <&dsi1_in_vp3>; __overlay__ { status = "okay"; - connect = <&vp3_out_dsi1>; }; }; fragment@6 { - target = <&i2c7>; + target = <&mipi_dcphy1>; __overlay__ { status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c6>; - gt9xx_0: touchscreen@14 { - compatible = "goodix,gt9271"; - reg = <0x14>; - interrupt-parent = <&gpio2>; - interrupts = ; - irq-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <1080>; - touchscreen-size-y = <1920>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx_dsi1: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + max-x = <1024>; + max-y = <600>; + tp-size = <2059>; + tp-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_dsi1_gpio>; status = "okay"; }; }; }; - fragment@7 { + fragment@8 { target = <&pinctrl>; __overlay__ { lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + lcd_dsi1_rst_gpio: lcd-dsi1-rst-gpio { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_dsi1_gpio: touch-dsi1-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts new file mode 100644 index 0000000000000..f0d0b1efdea53 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts @@ -0,0 +1,224 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/* + * Youyeetoo YY3588 - RK3588 + * 11.6" 1920x1080 LCD on eDP1 (GT928 touch) + */ + +/ { + metadata { + title = "Enable eDP Display on Youyeetoo YY3588"; + compatible = "youyeetoo,yy3588"; + category = "display"; + description = "Enable 11.6 inch 1920x1080 eDP display with GT928 touchscreen"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + backlight_edp: backlight-edp { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm15 0 25000 0>; + power-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vcc3v3_lcd: vcc3v3-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + vin-supply = <&vcc_3v3_s0>; + }; + + panel_edp1: panel-edp1 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd>; + /* Panel enable pad GPIO0_C4 is already held high by the + * always-on wifi_disable regulator in the board DTS. + */ + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <256>; + height-mm = <144>; + status = "okay"; + + panel-timing { + clock-frequency = <141500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <100>; + hsync-len = <22>; + hback-porch = <100>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp1: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&pwm15>; + + __overlay__ { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m2_pins>; + }; + }; + + fragment@2 { + target = <&edp1>; + + __overlay__ { + status = "okay"; + force-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp1>; + }; + }; + }; + }; + }; + + fragment@3 { + target = <&hdptxphy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&edp1_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&edp1_in_vp1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&edp1_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@7 { + target = <&route_edp1>; + + __overlay__ { + status = "okay"; + connect = <&vp1_out_edp1>; + }; + }; + + fragment@8 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx_edp: gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + touch-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + max-x = <1920>; + max-y = <1080>; + tp-size = <928>; + tp-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_edp_gpio>; + status = "okay"; + }; + }; + }; + + fragment@9 { + target = <&pinctrl>; + + __overlay__ { + lcd { + touch_edp_gpio: touch-edp-gpio { + rockchip,pins = + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; +}; From 5c7219dee9d531fe501d03b280a69839203bffd2 Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sat, 4 Jul 2026 23:26:03 +0200 Subject: [PATCH 29/32] arm64: dts: rockchip: overlay: youyeetoo: invert DSI backlight PWM The 7" kit backlight driver is active-low: with normal polarity raising brightness dims the panel, confirmed on R1 hardware. The vendor Android DTB programs the same PWM inverted. Flip polarity on all four DSI overlays; the eDP backlight stays normal per vendor. Signed-off-by: SuperKali --- .../boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts | 2 +- .../boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts | 2 +- .../boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts | 2 +- .../boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts index ec3e07d63a03e..a9aa974c416c0 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts @@ -52,7 +52,7 @@ 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; - pwms = <&pwm12 0 25000 0>; + pwms = <&pwm12 0 25000 1>; status = "okay"; power-supply = <&vcc5v0_sys>; }; diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts index 63b34e06daed9..c3f7fd24d692a 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi1.dts @@ -52,7 +52,7 @@ 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; - pwms = <&pwm11 0 25000 0>; + pwms = <&pwm11 0 25000 1>; status = "okay"; power-supply = <&vcc5v0_sys>; }; diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts index 5586bb7f20575..ecf6e330bbbfd 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts @@ -59,7 +59,7 @@ 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; - pwms = <&pwm1 0 25000 0>; + pwms = <&pwm1 0 25000 1>; power-supply = <&vcc5v0_sys>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts index 77f3f1cc29943..f0bc07f205467 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts @@ -59,7 +59,7 @@ 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; - pwms = <&pwm0 0 25000 0>; + pwms = <&pwm0 0 25000 1>; power-supply = <&vcc5v0_sys>; status = "okay"; }; From 7a6f183f641fa8d97dc4fae1ce251aa1619f785a Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sun, 5 Jul 2026 11:54:02 +0200 Subject: [PATCH 30/32] arm64: dts: rockchip: overlay: yy3588: fix eDP video port and timing eDP on VP1 fails: VP1 shares its PLL with VP0 so the 141.5MHz dclk gets clamped to 132MHz and the VOP2 port mux times out on the second modeset. Move eDP to VP2 as the vendor does and hand DP VP1 instead. Use the BOE QV116FHB-N81 datasheet typical timing and drop the panel enable GPIO, GPIO0_C4 is already held high by the always-on wifi_disable regulator in the board DTS. Signed-off-by: SuperKali --- .../overlay/youyeetoo-yy3588-display-edp.dts | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts index f0d0b1efdea53..31e91a2f184df 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts @@ -14,7 +14,7 @@ title = "Enable eDP Display on Youyeetoo YY3588"; compatible = "youyeetoo,yy3588"; category = "display"; - description = "Enable 11.6 inch 1920x1080 eDP display with GT928 touchscreen"; + description = "Enable 11.6 inch 1920x1080 eDP display with GT928 touchscreen. The panel HPD line is not wired (force-hpd), enable this overlay only with the panel connected or the display subsystem stalls at boot"; }; fragment@0 { @@ -84,6 +84,9 @@ height-mm = <144>; status = "okay"; + /* BOE QV116FHB-N81 datasheet typical timing. The EDID + * preferred 147.7MHz mode flickers on this eDP link. + */ panel-timing { clock-frequency = <141500000>; hactive = <1920>; @@ -161,7 +164,7 @@ target = <&edp1_in_vp1>; __overlay__ { - status = "okay"; + status = "disabled"; }; }; @@ -169,7 +172,7 @@ target = <&edp1_in_vp2>; __overlay__ { - status = "disabled"; + status = "okay"; }; }; @@ -178,7 +181,26 @@ __overlay__ { status = "okay"; - connect = <&vp1_out_edp1>; + connect = <&vp2_out_edp1>; + }; + }; + + /* dp0 owns VP2 in the board DTS; hand it VP1 so eDP can use VP2, + * matching the vendor VOP port mux arrangement. + */ + fragment@10 { + target = <&dp0_in_vp2>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@11 { + target = <&dp0_in_vp1>; + + __overlay__ { + status = "okay"; }; }; From e9dd0ea128a43ecf2c347a1e609bc202d48d8e96 Mon Sep 17 00:00:00 2001 From: SuperKali Date: Sun, 5 Jul 2026 11:54:03 +0200 Subject: [PATCH 31/32] arm64: dts: rockchip: overlay: yy3588: note panel requirement in overlays With the vendor kernel the display-subsystem bind stalls at boot when a display overlay is enabled without its panel attached, on eDP the forced HPD keeps link training against a missing sink. State the constraint in the overlay descriptions. Signed-off-by: SuperKali --- .../boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts | 2 +- .../boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts index ecf6e330bbbfd..1d6de2b3afe1d 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi0.dts @@ -15,7 +15,7 @@ title = "Enable DSI0 Display on Youyeetoo YY3588"; compatible = "youyeetoo,yy3588"; category = "display"; - description = "Enable 7 inch 1024x600 MIPI DSI0 display with GT911 touchscreen"; + description = "Enable 7 inch 1024x600 MIPI DSI0 display with GT911 touchscreen. Enable this overlay only with the panel connected or the display subsystem stalls at boot"; }; fragment@0 { diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts index f0bc07f205467..c8228f0955e18 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-dsi1.dts @@ -15,7 +15,7 @@ title = "Enable DSI1 Display on Youyeetoo YY3588"; compatible = "youyeetoo,yy3588"; category = "display"; - description = "Enable 7 inch 1024x600 MIPI DSI1 display with GT911 touchscreen"; + description = "Enable 7 inch 1024x600 MIPI DSI1 display with GT911 touchscreen. Enable this overlay only with the panel connected or the display subsystem stalls at boot"; }; fragment@0 { From b6e4a9275a13a84f178e32c9837cde3d82fe5f2f Mon Sep 17 00:00:00 2001 From: SuperKali Date: Tue, 7 Jul 2026 10:27:27 +0200 Subject: [PATCH 32/32] arm64: dts: rockchip: overlay: yy3588: disable eDP overlay temporarily The 11.6 inch eDP kit panel currently available shows severe image retention and can hang the display-subsystem bind as it degrades, so the overlay cannot be validated on known-good hardware right now. Rename it to .disabled and drop it from the overlay Makefile so it is not built or offered until a working panel is available to re-verify the path. Signed-off-by: SuperKali --- ...-display-edp.dts => youyeetoo-yy3588-display-edp.dts.disabled} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/arm64/boot/dts/rockchip/overlay/{youyeetoo-yy3588-display-edp.dts => youyeetoo-yy3588-display-edp.dts.disabled} (100%) diff --git a/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts b/arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts.disabled similarity index 100% rename from arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts rename to arch/arm64/boot/dts/rockchip/overlay/youyeetoo-yy3588-display-edp.dts.disabled