diff --git a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
index 216971b17..e9a1ac688 100644
--- a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
+++ b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20009000 EMPTY 0x00007000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
index 216971b17..e9a1ac688 100644
--- a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
+++ b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20009000 EMPTY 0x00007000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
index 216971b17..e9a1ac688 100644
--- a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
+++ b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20009000 EMPTY 0x00007000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf b/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf
index 63e2ebfcf..ca93a3d5e 100644
--- a/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf
+++ b/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf
@@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08020000;
 /*-Memory Regions-*/
 /***** FLASH part dedicated to M0+ *****/
 define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803EFFF;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
 /***** SRAM2 shared allocated by M0+ *****/
 define symbol __ICFEDIT_region_RAM2_SHARED_start__ = 0x20009000;
 define symbol __ICFEDIT_region_RAM2_SHARED_end__   = 0x20009FFF;
diff --git a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf
index 792caec13..d9178cc8e 100644
--- a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf
+++ b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf
@@ -13,7 +13,7 @@ define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
 define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
 /***** Backup SRAM2 dedicated to M4 *****/
 define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000BFFF;
+define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
 
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x4000; /*0x400;*/
diff --git a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct
index 17a17cf0e..04e5ca9e7 100644
--- a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct
+++ b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x0000C000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf b/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
index 4300afe92..0c58f4f44 100644
--- a/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
+++ b/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
@@ -7,13 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000;
 /*-Memory Regions-*/
 /***** FLASH part dedicated to M4 *****/
 define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0801FFFF;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
 /***** Non-backup SRAM1 dedicated to M4 *****/
 define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
 /***** Backup SRAM2 dedicated to M4 *****/
 define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000BFFF;
+define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
 
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x400;
diff --git a/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
index b04e7fea4..04e5ca9e7 100644
--- a/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
+++ b/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
@@ -2,18 +2,18 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
   ; FLASH part dedicated to M4
-  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
   ; Non-backup SRAM1 dedicated to M4
-  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld b/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
index 57981e6b4..3b63a26b3 100644
--- a/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
+++ b/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
@@ -16,9 +16,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Memories definition */
 MEMORY
 {
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K   /* Flash memory dedicated to CM4 */
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 dedicated to CM4 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 dedicated to CM4 */
 }
 
 /* Sections */
diff --git a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
index 4300afe92..0c58f4f44 100644
--- a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
+++ b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
@@ -7,13 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000;
 /*-Memory Regions-*/
 /***** FLASH part dedicated to M4 *****/
 define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0801FFFF;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
 /***** Non-backup SRAM1 dedicated to M4 *****/
 define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
 /***** Backup SRAM2 dedicated to M4 *****/
 define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000BFFF;
+define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
 
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x400;
diff --git a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
index b04e7fea4..04e5ca9e7 100644
--- a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
+++ b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
@@ -2,18 +2,18 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
   ; FLASH part dedicated to M4
-  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
   ; Non-backup SRAM1 dedicated to M4
-  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
index 57981e6b4..3b63a26b3 100644
--- a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
+++ b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
@@ -16,9 +16,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Memories definition */
 MEMORY
 {
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K   /* Flash memory dedicated to CM4 */
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 dedicated to CM4 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 dedicated to CM4 */
 }
 
 /* Sections */
diff --git a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
index 216971b17..e9a1ac688 100644
--- a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
+++ b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20009000 EMPTY 0x00007000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
index 216971b17..e9a1ac688 100644
--- a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
+++ b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20009000 EMPTY 0x00007000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
index 216971b17..e9a1ac688 100644
--- a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
+++ b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
@@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
    .ANY (+RW +ZI)
   }
   ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  RW_IRAM2 0x20009000 EMPTY 0x00007000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
   }
 }
diff --git a/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf b/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf
index 745c35790..c6834fb7a 100644
--- a/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf
+++ b/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf
@@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08020000;
 /*-Memory Regions-*/
 /***** FLASH part dedicated to M0+ *****/
 define symbol __ICFEDIT_region_ROM_start__    = 0x08020000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0803EFFF;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
 /***** SRAM2 shared allocated by M0+ *****/
 define symbol __ICFEDIT_region_RAM2_SHARED_start__ = 0x20009000;
 define symbol __ICFEDIT_region_RAM2_SHARED_end__   = 0x20009FFF;
diff --git a/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld b/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
index 65cba0c78..dad8d69b5 100644
--- a/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
+++ b/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
@@ -14,10 +14,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Memories definition */
 MEMORY
 {
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
-  RAM   (xrw)    : ORIGIN = 0x20002000, LENGTH  = 16K
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K   /* Flash memory dedicated to CM4 */
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 dedicated to CM4 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 dedicated to CM4 */
 }
 
 /* Sections */
@@ -118,10 +117,10 @@ SECTIONS
     
   } >RAM1 AT> ROM
   
-  .ROarraySection (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  .ROarraySection 0x20002000 (READONLY) : /* fixed address: matches ARRAY_ADDRESS_START in stm32_mpu.c and the IAR #pragma location. The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
   {
     *(.ROarraySection*)
-  } >RAM
+  } >RAM1
  
   /* Uninitialized data section into "SRAM1" Ram type memory */
   . = ALIGN(8);
diff --git a/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld b/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
index ff69c38bf..63a9a4f0c 100644
--- a/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
+++ b/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
@@ -15,8 +15,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 MEMORY
 {
   ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
-  RAM   (xrw)    : ORIGIN = 0x20002000, LENGTH = 16K
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 dedicated to CM4 */
   RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 */
 }
 
@@ -118,10 +117,10 @@ SECTIONS
     
   } >RAM1 AT> ROM
   
-  .ROarraySection (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  .ROarraySection 0x20002000 (READONLY) : /* fixed address: matches ARRAY_ADDRESS_START in main.c and the IAR #pragma location. The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
   {
     *(.ROarraySection*)
-  } >RAM
+  } >RAM1
  
   /* Uninitialized data section into "SRAM1" Ram type memory */
   . = ALIGN(8);