From 857c003b96214fbb8150e8ede76f5fb14e8fea44 Mon Sep 17 00:00:00 2001 From: yi chen <94xhn1@gmail.com> Date: Sat, 11 Jul 2026 07:50:04 +0800 Subject: [PATCH] fix(linker): correct several cross-toolchain memory map inconsistencies Found by cross-checking each example's GCC (STM32CubeIDE)/IAR (EWARM)/ Keil (MDK-ARM) linker scripts against each other and against known-good sibling projects for the same chip. Five independent issues, all in Projects/: 1. SubGHz_Phy_PingPong_DualCore (CM0+, both boards): EWARM's .icf under-declares FLASH by exactly 4096 bytes (0x0803EFFF instead of 0x0803FFFF), while MDK-ARM and STM32CubeIDE both correctly use the full 128K for this core's flash half. 2. CORTEX(M)_MPU (CM4, NUCLEO-WL55JC, both Examples and Examples_LL variants): STM32CubeIDE's .ld used a DualCore-style half-chip memory map (128K ROM instead of 256K, 16K RAM1/RAM2 instead of 32K/32K) for what is a single-core-only example, and additionally declared an extra `RAM` region at 0x20002000 that overlapped RAM1 by 8K while leaving another 8K completely unmapped. Confirmed via the example's own MPU_Config()/MPU_AccessPermConfig() in Src/stm32_mpu.c (or Src/main.c for the LL variant), whose own macros (EXAMPLE_FLASH_SIZE=256KB, EXAMPLE_RAM_SIZE=64KB, ARRAY_ADDRESS_START=0x20002000) match EWARM/MDK-ARM's existing correct values exactly, proving STM32CubeIDE's map was wrong, not a deliberate restriction. Fixed by using the correct 256K/32K/32K split and placing `.ROarraySection` at the required fixed address (0x20002000, matching the IAR #pragma location) inside the corrected, non-overlapping RAM1 region instead of a separate overlapping region. 3. LocalNetwork_Sensor/Sensor (CM4, B-WL5M-SUBG1): RAM2 disagreed 3 ways - EWARM declared 16K, MDK-ARM declared 48K (larger than the chip's actual SRAM2), STM32CubeIDE correctly declared 32K. Fixed EWARM and MDK-ARM to match the correct 32K. 4. LoRaWAN_End_Node_LBM / LoRaWAN_End_Node_Relay_LBM / LoRaWAN_Relay_LBM (CM4, both boards, 6 files): MDK-ARM's RW_IRAM2 started immediately after RAM1 (0x20008000) with only 16K, while EWARM and STM32CubeIDE both correctly reserve a 4K gap (0x20008000-0x20008FFF, used as NVM_RAM in the GCC script) before a 28K RAM2 starting at 0x20009000. MDK's version both encroached on the reserved gap and lost the last 16K of physical SRAM2. Fixed to start RAM2 at 0x20009000 with 28K, matching EWARM/GCC exactly. 5. Templates/SingleCore and Templates_LL/SingleCore (CM4, B-WL5M-SUBG1, 6 files): all three toolchains agreed with each other here, but on the wrong value - byte-for-byte identical to this board's Templates/DualCore/CM4 (128K ROM, 16K RAM1, 16K RAM2) instead of the correct full single-core memory map (256K ROM, 32K RAM1, 32K RAM2). Confirmed against the sibling NUCLEO-WL55JC's correct Templates/SingleCore (all 3 toolchains agree there) and against this board's own real single-core apps (e.g. the LoRaWAN family above, which use the full 256K/32K/32K split). Fixed all 3 toolchain files in both directories to the correct values. No local ARM toolchain available to compile/link-test these changes, so verification relied on careful address-arithmetic cross-referencing against multiple independent, already-correct references for each finding (sibling toolchain files of the same project, sibling board's equivalent project, and - for finding 2 - the example's own MPU configuration source code). Signed-off-by: yi chen <94xhn1@gmail.com> --- .../MDK-ARM/stm32wl5mxx_flash_cm4.sct | 2 +- .../MDK-ARM/stm32wl5mxx_flash_cm4.sct | 2 +- .../MDK-ARM/stm32wl5mxx_flash_cm4.sct | 2 +- .../EWARM/stm32wl5mxx_flash_cm0plus.icf | 2 +- .../Sensor/EWARM/stm32wl5mxx_flash_cm4.icf | 2 +- .../Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct | 2 +- .../SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf | 6 +++--- .../SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct | 8 ++++---- .../SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld | 6 +++--- .../SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf | 6 +++--- .../SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct | 8 ++++---- .../SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld | 6 +++--- .../MDK-ARM/stm32wl55xx_flash_cm4.sct | 2 +- .../MDK-ARM/stm32wl55xx_flash_cm4.sct | 2 +- .../MDK-ARM/stm32wl55xx_flash_cm4.sct | 2 +- .../EWARM/stm32wl55xx_flash_cm0plus.icf | 2 +- .../CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld | 11 +++++------ .../CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld | 7 +++---- 18 files changed, 38 insertions(+), 40 deletions(-) diff --git a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct index 216971b17..e9a1ac688 100644 --- a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct +++ b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct index 216971b17..e9a1ac688 100644 --- a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct +++ b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct index 216971b17..e9a1ac688 100644 --- a/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct +++ b/Projects/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf b/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf index 63e2ebfcf..ca93a3d5e 100644 --- a/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf +++ b/Projects/B-WL5M-SUBG1/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08020000; /*-Memory Regions-*/ /***** FLASH part dedicated to M0+ *****/ define symbol __ICFEDIT_region_ROM_start__ = 0x08020000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0803EFFF; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; /***** SRAM2 shared allocated by M0+ *****/ define symbol __ICFEDIT_region_RAM2_SHARED_start__ = 0x20009000; define symbol __ICFEDIT_region_RAM2_SHARED_end__ = 0x20009FFF; diff --git a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf index 792caec13..d9178cc8e 100644 --- a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf +++ b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf @@ -13,7 +13,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; /***** Backup SRAM2 dedicated to M4 *****/ define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; -define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x4000; /*0x400;*/ diff --git a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct index 17a17cf0e..04e5ca9e7 100644 --- a/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct +++ b/Projects/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x0000C000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf b/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf index 4300afe92..0c58f4f44 100644 --- a/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf +++ b/Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf @@ -7,13 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ /***** FLASH part dedicated to M4 *****/ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; /***** Non-backup SRAM1 dedicated to M4 *****/ define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; /***** Backup SRAM2 dedicated to M4 *****/ define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; -define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; diff --git a/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct index b04e7fea4..04e5ca9e7 100644 --- a/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct +++ b/Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct @@ -2,18 +2,18 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x00020000 { ; load region size_region +LR_IROM1 0x08000000 0x00040000 { ; load region size_region ; FLASH part dedicated to M4 - ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } ; Non-backup SRAM1 dedicated to M4 - RW_IRAM1 0x20000000 0x00004000 { ; RW data + RW_IRAM1 0x20000000 0x00008000 { ; RW data .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld b/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld index 57981e6b4..3b63a26b3 100644 --- a/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld +++ b/Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld @@ -16,9 +16,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */ - RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */ - RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */ + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */ } /* Sections */ diff --git a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf index 4300afe92..0c58f4f44 100644 --- a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf +++ b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf @@ -7,13 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ /***** FLASH part dedicated to M4 *****/ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; /***** Non-backup SRAM1 dedicated to M4 *****/ define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; /***** Backup SRAM2 dedicated to M4 *****/ define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; -define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; diff --git a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct index b04e7fea4..04e5ca9e7 100644 --- a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct +++ b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct @@ -2,18 +2,18 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x00020000 { ; load region size_region +LR_IROM1 0x08000000 0x00040000 { ; load region size_region ; FLASH part dedicated to M4 - ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } ; Non-backup SRAM1 dedicated to M4 - RW_IRAM1 0x20000000 0x00004000 { ; RW data + RW_IRAM1 0x20000000 0x00008000 { ; RW data .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld index 57981e6b4..3b63a26b3 100644 --- a/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld +++ b/Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld @@ -16,9 +16,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */ - RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */ - RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */ + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */ } /* Sections */ diff --git a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct index 216971b17..e9a1ac688 100644 --- a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct +++ b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct index 216971b17..e9a1ac688 100644 --- a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct +++ b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct index 216971b17..e9a1ac688 100644 --- a/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct +++ b/Projects/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region .ANY (+RW +ZI) } ; Backup SRAM2 dedicated to M4 - RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... } } diff --git a/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf b/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf index 745c35790..c6834fb7a 100644 --- a/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf +++ b/Projects/NUCLEO-WL55JC/Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08020000; /*-Memory Regions-*/ /***** FLASH part dedicated to M0+ *****/ define symbol __ICFEDIT_region_ROM_start__ = 0x08020000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0803EFFF; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; /***** SRAM2 shared allocated by M0+ *****/ define symbol __ICFEDIT_region_RAM2_SHARED_start__ = 0x20009000; define symbol __ICFEDIT_region_RAM2_SHARED_end__ = 0x20009FFF; diff --git a/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld b/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld index 65cba0c78..dad8d69b5 100644 --- a/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld +++ b/Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld @@ -14,10 +14,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */ - RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 16K - RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */ + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */ } /* Sections */ @@ -118,10 +117,10 @@ SECTIONS } >RAM1 AT> ROM - .ROarraySection (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + .ROarraySection 0x20002000 (READONLY) : /* fixed address: matches ARRAY_ADDRESS_START in stm32_mpu.c and the IAR #pragma location. The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ROarraySection*) - } >RAM + } >RAM1 /* Uninitialized data section into "SRAM1" Ram type memory */ . = ALIGN(8); diff --git a/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld b/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld index ff69c38bf..63a9a4f0c 100644 --- a/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld +++ b/Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld @@ -15,8 +15,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ MEMORY { ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K - RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */ - RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 16K + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */ RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 */ } @@ -118,10 +117,10 @@ SECTIONS } >RAM1 AT> ROM - .ROarraySection (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + .ROarraySection 0x20002000 (READONLY) : /* fixed address: matches ARRAY_ADDRESS_START in main.c and the IAR #pragma location. The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ROarraySection*) - } >RAM + } >RAM1 /* Uninitialized data section into "SRAM1" Ram type memory */ . = ALIGN(8);