cache_sim

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2009.vpi";
S_0000026f26f14950 .scope package, "$unit" "$unit" 2 1;
 .timescale 0 0;
S_0000026f26f779e0 .scope module, "tb_direct_mapped_cache" "tb_direct_mapped_cache" 3 2;
 .timescale -9 -12;
P_0000026f26f78540 .param/l "ADDR_WIDTH" 0 3 4, +C4<00000000000000000000000000100000>;
P_0000026f26f78578 .param/l "BLOCKS" 0 3 6, +C4<00000000000000000000000000010000>;
P_0000026f26f785b0 .param/l "DATA_WIDTH" 0 3 5, +C4<00000000000000000000000000100000>;
P_0000026f26f785e8 .param/l "MEM_WORDS" 0 3 7, +C4<00000000000000000000000100000000>;
v0000026f26fd8cc0_0 .var "clk", 0 0;
v0000026f26fd8ae0_0 .var "cpu_addr", 31 0;
v0000026f26fd8220_0 .net "cpu_rdata", 31 0, v0000026f26f6e650_0;  1 drivers
v0000026f26fd8360_0 .net "cpu_ready", 0 0, v0000026f26f6ebf0_0;  1 drivers
v0000026f26fd9260_0 .var "cpu_req", 0 0;
v0000026f26fd8d60_0 .var "cpu_wdata", 31 0;
v0000026f26fd84a0_0 .var "cpu_write", 0 0;
v0000026f26fd8540_0 .var/i "fail_count", 31 0;
v0000026f26fd8e00_0 .net "mem_addr", 31 0, v0000026f26fccb10_0;  1 drivers
v0000026f26fd8ea0_0 .net "mem_rdata", 31 0, v0000026f26fd8680_0;  1 drivers
v0000026f26fd9300_0 .net "mem_ready", 0 0, v0000026f26fd9440_0;  1 drivers
v0000026f26fd8720_0 .net "mem_req", 0 0, v0000026f26fcd010_0;  1 drivers
v0000026f26fd87c0_0 .net "mem_wdata", 31 0, v0000026f26fcc7f0_0;  1 drivers
v0000026f26fd93a0_0 .net "mem_write", 0 0, v0000026f26fccf70_0;  1 drivers
v0000026f26fdb9f0_0 .var/i "pass_count", 31 0;
v0000026f26fdb130_0 .var "reset", 0 0;
S_0000026f26f7be20 .scope module, "DUT" "direct_mapped_cache" 3 41, 4 1 0, S_0000026f26f779e0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /INPUT 1 "cpu_req";
    .port_info 3 /INPUT 1 "cpu_write";
    .port_info 4 /INPUT 32 "cpu_addr";
    .port_info 5 /INPUT 32 "cpu_wdata";
    .port_info 6 /OUTPUT 32 "cpu_rdata";
    .port_info 7 /OUTPUT 1 "cpu_ready";
    .port_info 8 /OUTPUT 1 "mem_req";
    .port_info 9 /OUTPUT 1 "mem_write";
    .port_info 10 /OUTPUT 32 "mem_addr";
    .port_info 11 /OUTPUT 32 "mem_wdata";
    .port_info 12 /INPUT 32 "mem_rdata";
    .port_info 13 /INPUT 1 "mem_ready";
P_0000026f26f4edf0 .param/l "ADDR_WIDTH" 0 4 2, +C4<00000000000000000000000000100000>;
P_0000026f26f4ee28 .param/l "BLOCKS" 0 4 4, +C4<00000000000000000000000000010000>;
P_0000026f26f4ee60 .param/l "DATA_WIDTH" 0 4 3, +C4<00000000000000000000000000100000>;
P_0000026f26f4ee98 .param/l "INDEX_WIDTH" 0 4 5, +C4<00000000000000000000000000000100>;
P_0000026f26f4eed0 .param/l "OFFSET_WIDTH" 0 4 6, +C4<00000000000000000000000000000010>;
P_0000026f26f4ef08 .param/l "TAG_WIDTH" 0 4 7, +C4<0000000000000000000000000000011010>;
v0000026f26fccd90_0 .net "cache_data", 31 0, L_0000026f26f64880;  1 drivers
v0000026f26fcd290_0 .net "cache_data_in", 31 0, v0000026f26f6f050_0;  1 drivers
v0000026f26fcd330_0 .net "cache_dirty", 0 0, L_0000026f26f64500;  1 drivers
v0000026f26fcd3d0_0 .net "cache_dirty_in", 0 0, v0000026f26f6eab0_0;  1 drivers
v0000026f26fcd470_0 .net "cache_index", 3 0, L_0000026f26f64490;  1 drivers
v0000026f26fcd5b0_0 .net "cache_tag", 25 0, L_0000026f26f647a0;  1 drivers
v0000026f26fcdb50_0 .net "cache_tag_in", 25 0, v0000026f26f6ea10_0;  1 drivers
v0000026f26fcdbf0_0 .net "cache_valid", 0 0, L_0000026f26f648f0;  1 drivers
v0000026f26fd9d00_0 .net "cache_valid_in", 0 0, v0000026f26f6f0f0_0;  1 drivers
v0000026f26fd96c0_0 .net "cache_write_en", 0 0, v0000026f26f6e790_0;  1 drivers
v0000026f26fd9760_0 .net "clk", 0 0, v0000026f26fd8cc0_0;  1 drivers
v0000026f26fd9bc0_0 .net "cpu_addr", 31 0, v0000026f26fd8ae0_0;  1 drivers
v0000026f26fd94e0_0 .net "cpu_rdata", 31 0, v0000026f26f6e650_0;  alias, 1 drivers
v0000026f26fd89a0_0 .net "cpu_ready", 0 0, v0000026f26f6ebf0_0;  alias, 1 drivers
v0000026f26fd85e0_0 .net "cpu_req", 0 0, v0000026f26fd9260_0;  1 drivers
v0000026f26fd9da0_0 .net "cpu_wdata", 31 0, v0000026f26fd8d60_0;  1 drivers
v0000026f26fd9080_0 .net "cpu_write", 0 0, v0000026f26fd84a0_0;  1 drivers
v0000026f26fd9e40_0 .net "mem_addr", 31 0, v0000026f26fccb10_0;  alias, 1 drivers
v0000026f26fd8860_0 .net "mem_rdata", 31 0, v0000026f26fd8680_0;  alias, 1 drivers
v0000026f26fd8b80_0 .net "mem_ready", 0 0, v0000026f26fd9440_0;  alias, 1 drivers
v0000026f26fd9800_0 .net "mem_req", 0 0, v0000026f26fcd010_0;  alias, 1 drivers
v0000026f26fd8900_0 .net "mem_wdata", 31 0, v0000026f26fcc7f0_0;  alias, 1 drivers
v0000026f26fd82c0_0 .net "mem_write", 0 0, v0000026f26fccf70_0;  alias, 1 drivers
v0000026f26fd8a40_0 .net "reset", 0 0, v0000026f26fdb130_0;  1 drivers
S_0000026f26f4ef50 .scope module, "cache_controller_inst" "cache_controller" 4 79, 5 1 0, S_0000026f26f7be20;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /INPUT 1 "cpu_req";
    .port_info 3 /INPUT 1 "cpu_write";
    .port_info 4 /INPUT 32 "cpu_addr";
    .port_info 5 /INPUT 32 "cpu_wdata";
    .port_info 6 /OUTPUT 32 "cpu_rdata";
    .port_info 7 /OUTPUT 1 "cpu_ready";
    .port_info 8 /OUTPUT 4 "cache_index";
    .port_info 9 /INPUT 26 "cache_tag";
    .port_info 10 /INPUT 32 "cache_data";
    .port_info 11 /INPUT 1 "cache_valid";
    .port_info 12 /INPUT 1 "cache_dirty";
    .port_info 13 /OUTPUT 1 "cache_write_en";
    .port_info 14 /OUTPUT 26 "cache_tag_in";
    .port_info 15 /OUTPUT 32 "cache_data_in";
    .port_info 16 /OUTPUT 1 "cache_valid_in";
    .port_info 17 /OUTPUT 1 "cache_dirty_in";
    .port_info 18 /OUTPUT 1 "mem_req";
    .port_info 19 /OUTPUT 1 "mem_write";
    .port_info 20 /OUTPUT 32 "mem_addr";
    .port_info 21 /OUTPUT 32 "mem_wdata";
    .port_info 22 /INPUT 32 "mem_rdata";
    .port_info 23 /INPUT 1 "mem_ready";
P_0000026f26f42b40 .param/l "ADDR_WIDTH" 0 5 2, +C4<00000000000000000000000000100000>;
P_0000026f26f42b78 .param/l "ALLOCATE" 1 5 48, C4<011>;
P_0000026f26f42bb0 .param/l "BLOCKS" 0 5 4, +C4<00000000000000000000000000010000>;
P_0000026f26f42be8 .param/l "DATA_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
P_0000026f26f42c20 .param/l "IDLE" 1 5 45, C4<000>;
P_0000026f26f42c58 .param/l "INDEX_WIDTH" 0 5 5, +C4<00000000000000000000000000000100>;
P_0000026f26f42c90 .param/l "LOOKUP" 1 5 46, C4<001>;
P_0000026f26f42cc8 .param/l "OFFSET_WIDTH" 0 5 6, +C4<00000000000000000000000000000010>;
P_0000026f26f42d00 .param/l "TAG_WIDTH" 0 5 7, +C4<0000000000000000000000000000011010>;
P_0000026f26f42d38 .param/l "UPDATE" 1 5 49, C4<100>;
P_0000026f26f42d70 .param/l "WRITE_BACK" 1 5 47, C4<010>;
L_0000026f26f64490 .functor BUFZ 4, L_0000026f26fdb6d0, C4<0000>, C4<0000>, C4<0000>;
L_0000026f26f64c70 .functor AND 1, L_0000026f26f648f0, L_0000026f26fdbf90, C4<1>, C4<1>;
v0000026f26f6e330_0 .net *"_ivl_6", 0 0, L_0000026f26fdbf90;  1 drivers
v0000026f26f6e1f0_0 .net "cache_data", 31 0, L_0000026f26f64880;  alias, 1 drivers
v0000026f26f6f050_0 .var "cache_data_in", 31 0;
v0000026f26f6e3d0_0 .net "cache_dirty", 0 0, L_0000026f26f64500;  alias, 1 drivers
v0000026f26f6eab0_0 .var "cache_dirty_in", 0 0;
v0000026f26f6e830_0 .net "cache_hit", 0 0, L_0000026f26f64c70;  1 drivers
v0000026f26f6ef10_0 .net "cache_index", 3 0, L_0000026f26f64490;  alias, 1 drivers
v0000026f26f6e8d0_0 .net "cache_tag", 25 0, L_0000026f26f647a0;  alias, 1 drivers
v0000026f26f6ea10_0 .var "cache_tag_in", 25 0;
v0000026f26f6e470_0 .net "cache_valid", 0 0, L_0000026f26f648f0;  alias, 1 drivers
v0000026f26f6f0f0_0 .var "cache_valid_in", 0 0;
v0000026f26f6e790_0 .var "cache_write_en", 0 0;
v0000026f26f6ee70_0 .net "clk", 0 0, v0000026f26fd8cc0_0;  alias, 1 drivers
v0000026f26f6e290_0 .net "cpu_addr", 31 0, v0000026f26fd8ae0_0;  alias, 1 drivers
v0000026f26f6e650_0 .var "cpu_rdata", 31 0;
v0000026f26f6ebf0_0 .var "cpu_ready", 0 0;
v0000026f26f6e5b0_0 .net "cpu_req", 0 0, v0000026f26fd9260_0;  alias, 1 drivers
v0000026f26f6e6f0_0 .net "cpu_wdata", 31 0, v0000026f26fd8d60_0;  alias, 1 drivers
v0000026f26f6eb50_0 .net "cpu_write", 0 0, v0000026f26fd84a0_0;  alias, 1 drivers
v0000026f26fccb10_0 .var "mem_addr", 31 0;
v0000026f26fcd1f0_0 .net "mem_rdata", 31 0, v0000026f26fd8680_0;  alias, 1 drivers
v0000026f26fcdfb0_0 .net "mem_ready", 0 0, v0000026f26fd9440_0;  alias, 1 drivers
v0000026f26fcd010_0 .var "mem_req", 0 0;
v0000026f26fcc7f0_0 .var "mem_wdata", 31 0;
v0000026f26fccf70_0 .var "mem_write", 0 0;
v0000026f26fcd150_0 .var "req_addr", 31 0;
v0000026f26fcc930_0 .net "req_index", 3 0, L_0000026f26fdb6d0;  1 drivers
v0000026f26fccbb0_0 .net "req_tag", 25 0, L_0000026f26fdb310;  1 drivers
v0000026f26fcdd30_0 .var "req_wdata", 31 0;
v0000026f26fcdc90_0 .var "req_write", 0 0;
v0000026f26fcd830_0 .net "reset", 0 0, v0000026f26fdb130_0;  alias, 1 drivers
v0000026f26fcc9d0_0 .var "state", 2 0;
E_0000026f26f0fa80/0 .event anyedge, v0000026f26fcc9d0_0, v0000026f26fcdfb0_0, v0000026f26f6e8d0_0, v0000026f26fcc930_0;
E_0000026f26f0fa80/1 .event anyedge, v0000026f26f6e1f0_0, v0000026f26fccbb0_0;
E_0000026f26f0fa80 .event/or E_0000026f26f0fa80/0, E_0000026f26f0fa80/1;
E_0000026f26f117c0 .event posedge, v0000026f26f6ee70_0;
L_0000026f26fdb310 .part v0000026f26fcd150_0, 6, 26;
L_0000026f26fdb6d0 .part v0000026f26fcd150_0, 2, 4;
L_0000026f26fdbf90 .cmp/eq 26, L_0000026f26f647a0, L_0000026f26fdb310;
S_0000026f26f42db0 .scope module, "cache_memory_inst" "cache_memory" 4 56, 6 1 0, S_0000026f26f7be20;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /INPUT 4 "index";
    .port_info 3 /OUTPUT 26 "tag_out";
    .port_info 4 /OUTPUT 32 "data_out";
    .port_info 5 /OUTPUT 1 "valid_out";
    .port_info 6 /OUTPUT 1 "dirty_out";
    .port_info 7 /INPUT 1 "write_en";
    .port_info 8 /INPUT 26 "tag_in";
    .port_info 9 /INPUT 32 "data_in";
    .port_info 10 /INPUT 1 "valid_in";
    .port_info 11 /INPUT 1 "dirty_in";
P_0000026f26fced40 .param/l "ADDR_WIDTH" 0 6 2, +C4<00000000000000000000000000100000>;
P_0000026f26fced78 .param/l "BLOCKS" 0 6 4, +C4<00000000000000000000000000010000>;
P_0000026f26fcedb0 .param/l "DATA_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
P_0000026f26fcede8 .param/l "INDEX_WIDTH" 0 6 5, +C4<00000000000000000000000000000100>;
P_0000026f26fcee20 .param/l "OFFSET_WIDTH" 0 6 6, +C4<00000000000000000000000000000010>;
P_0000026f26fcee58 .param/l "TAG_WIDTH" 0 6 7, +C4<0000000000000000000000000000011010>;
L_0000026f26f647a0 .functor BUFZ 26, L_0000026f26fdba90, C4<00000000000000000000000000>, C4<00000000000000000000000000>, C4<00000000000000000000000000>;
L_0000026f26f64880 .functor BUFZ 32, L_0000026f26fdb090, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0000026f26f648f0 .functor BUFZ 1, L_0000026f26fdb450, C4<0>, C4<0>, C4<0>;
L_0000026f26f64500 .functor BUFZ 1, L_0000026f26fda230, C4<0>, C4<0>, C4<0>;
v0000026f26fce410_0 .net *"_ivl_0", 25 0, L_0000026f26fdba90;  1 drivers
v0000026f26fce2d0_0 .net *"_ivl_10", 5 0, L_0000026f26fda690;  1 drivers
L_0000026f26fdc100 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000026f26fcced0_0 .net *"_ivl_13", 1 0, L_0000026f26fdc100;  1 drivers
v0000026f26fcddd0_0 .net *"_ivl_16", 0 0, L_0000026f26fdb450;  1 drivers
v0000026f26fcde70_0 .net *"_ivl_18", 5 0, L_0000026f26fda190;  1 drivers
v0000026f26fcd790_0 .net *"_ivl_2", 5 0, L_0000026f26fdbb30;  1 drivers
L_0000026f26fdc148 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000026f26fcd650_0 .net *"_ivl_21", 1 0, L_0000026f26fdc148;  1 drivers
v0000026f26fcc750_0 .net *"_ivl_24", 0 0, L_0000026f26fda230;  1 drivers
v0000026f26fcce30_0 .net *"_ivl_26", 5 0, L_0000026f26fdab90;  1 drivers
L_0000026f26fdc190 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000026f26fcd6f0_0 .net *"_ivl_29", 1 0, L_0000026f26fdc190;  1 drivers
L_0000026f26fdc0b8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000026f26fce050_0 .net *"_ivl_5", 1 0, L_0000026f26fdc0b8;  1 drivers
v0000026f26fce370_0 .net *"_ivl_8", 31 0, L_0000026f26fdb090;  1 drivers
v0000026f26fcd0b0_0 .net "clk", 0 0, v0000026f26fd8cc0_0;  alias, 1 drivers
v0000026f26fcdf10 .array "data_array", 15 0, 31 0;
v0000026f26fce0f0_0 .net "data_in", 31 0, v0000026f26f6f050_0;  alias, 1 drivers
v0000026f26fce190_0 .net "data_out", 31 0, L_0000026f26f64880;  alias, 1 drivers
v0000026f26fcc890 .array "dirty_array", 15 0, 0 0;
v0000026f26fcc570_0 .net "dirty_in", 0 0, v0000026f26f6eab0_0;  alias, 1 drivers
v0000026f26fcdab0_0 .net "dirty_out", 0 0, L_0000026f26f64500;  alias, 1 drivers
v0000026f26fccc50_0 .var/i "i", 31 0;
v0000026f26fcd970_0 .net "index", 3 0, L_0000026f26f64490;  alias, 1 drivers
v0000026f26fcda10_0 .net "reset", 0 0, v0000026f26fdb130_0;  alias, 1 drivers
v0000026f26fce230 .array "tag_array", 15 0, 25 0;
v0000026f26fcc610_0 .net "tag_in", 25 0, v0000026f26f6ea10_0;  alias, 1 drivers
v0000026f26fcd510_0 .net "tag_out", 25 0, L_0000026f26f647a0;  alias, 1 drivers
v0000026f26fcc6b0 .array "valid_array", 15 0, 0 0;
v0000026f26fcccf0_0 .net "valid_in", 0 0, v0000026f26f6f0f0_0;  alias, 1 drivers
v0000026f26fcca70_0 .net "valid_out", 0 0, L_0000026f26f648f0;  alias, 1 drivers
v0000026f26fcd8d0_0 .net "write_en", 0 0, v0000026f26f6e790_0;  alias, 1 drivers
L_0000026f26fdba90 .array/port v0000026f26fce230, L_0000026f26fdbb30;
L_0000026f26fdbb30 .concat [ 4 2 0 0], L_0000026f26f64490, L_0000026f26fdc0b8;
L_0000026f26fdb090 .array/port v0000026f26fcdf10, L_0000026f26fda690;
L_0000026f26fda690 .concat [ 4 2 0 0], L_0000026f26f64490, L_0000026f26fdc100;
L_0000026f26fdb450 .array/port v0000026f26fcc6b0, L_0000026f26fda190;
L_0000026f26fda190 .concat [ 4 2 0 0], L_0000026f26f64490, L_0000026f26fdc148;
L_0000026f26fda230 .array/port v0000026f26fcc890, L_0000026f26fdab90;
L_0000026f26fdab90 .concat [ 4 2 0 0], L_0000026f26f64490, L_0000026f26fdc190;
S_0000026f26f1c760 .scope module, "MEMORY" "main_memory" 3 64, 7 3 0, S_0000026f26f779e0;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /INPUT 1 "mem_req";
    .port_info 3 /INPUT 1 "mem_write";
    .port_info 4 /INPUT 32 "mem_addr";
    .port_info 5 /INPUT 32 "mem_wdata";
    .port_info 6 /OUTPUT 32 "mem_rdata";
    .port_info 7 /OUTPUT 1 "mem_ready";
P_0000026f26f1c8f0 .param/l "ADDR_WIDTH" 0 7 4, +C4<00000000000000000000000000100000>;
P_0000026f26f1c928 .param/l "DATA_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>;
P_0000026f26f1c960 .param/l "LATENCY" 0 7 7, +C4<00000000000000000000000000000011>;
P_0000026f26f1c998 .param/l "MEM_AWIDTH" 0 7 9, +C4<00000000000000000000000000001000>;
P_0000026f26f1c9d0 .param/l "MEM_WORDS" 0 7 6, +C4<00000000000000000000000100000000>;
P_0000026f26f1ca08 .param/l "OFFSET_WIDTH" 0 7 8, +C4<00000000000000000000000000000010>;
v0000026f26fd9ee0_0 .var "busy", 0 0;
v0000026f26fd98a0_0 .net "clk", 0 0, v0000026f26fd8cc0_0;  alias, 1 drivers
v0000026f26fd9940_0 .var/i "counter", 31 0;
v0000026f26fd8fe0_0 .var/i "i", 31 0;
v0000026f26fd9f80_0 .net "mem_addr", 31 0, v0000026f26fccb10_0;  alias, 1 drivers
v0000026f26fd8680_0 .var "mem_rdata", 31 0;
v0000026f26fd9440_0 .var "mem_ready", 0 0;
v0000026f26fd8c20_0 .net "mem_req", 0 0, v0000026f26fcd010_0;  alias, 1 drivers
v0000026f26fd80e0_0 .net "mem_wdata", 31 0, v0000026f26fcc7f0_0;  alias, 1 drivers
v0000026f26fd9620_0 .net "mem_write", 0 0, v0000026f26fccf70_0;  alias, 1 drivers
v0000026f26fd9120 .array "memory", 255 0, 31 0;
v0000026f26fd99e0_0 .net "reset", 0 0, v0000026f26fdb130_0;  alias, 1 drivers
v0000026f26fd9c60_0 .var "saved_addr", 31 0;
v0000026f26fd9580_0 .var "saved_wdata", 31 0;
v0000026f26fd8400_0 .net "saved_word_addr", 7 0, L_0000026f26fdb770;  1 drivers
v0000026f26fd91c0_0 .var "saved_write", 0 0;
L_0000026f26fdb770 .part v0000026f26fd9c60_0, 2, 8;
S_0000026f26ee2d20 .scope task, "cpu_read" "cpu_read" 3 76, 3 76 0, S_0000026f26f779e0;
 .timescale -9 -12;
v0000026f26fd9a80_0 .var "address", 31 0;
v0000026f26fd9b20_0 .var "expected", 31 0;
E_0000026f26f10a40 .event negedge, v0000026f26f6ee70_0;
E_0000026f26f11400 .event anyedge, v0000026f26f6ebf0_0;
TD_tb_direct_mapped_cache.cpu_read ;
    %wait E_0000026f26f10a40;
    %load/vec4 v0000026f26fd9a80_0;
    %store/vec4 v0000026f26fd8ae0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd8d60_0, 0, 32;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fd84a0_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fd9260_0, 0, 1;
    %wait E_0000026f26f10a40;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fd9260_0, 0, 1;
T_0.0 ;
    %load/vec4 v0000026f26fd8360_0;
    %pushi/vec4 1, 0, 1;
    %cmp/e;
    %flag_get/vec4 4;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_0.1, 6;
    %wait E_0000026f26f11400;
    %jmp T_0.0;
T_0.1 ;
    %load/vec4 v0000026f26fd8220_0;
    %load/vec4 v0000026f26fd9b20_0;
    %cmp/e;
    %jmp/0xz  T_0.2, 6;
    %vpi_call/w 3 92 "$display", "[PASS] READ addr=%h data=%h", v0000026f26fd9a80_0, v0000026f26fd8220_0 {0 0 0};
    %load/vec4 v0000026f26fdb9f0_0;
    %addi 1, 0, 32;
    %store/vec4 v0000026f26fdb9f0_0, 0, 32;
    %jmp T_0.3;
T_0.2 ;
    %vpi_call/w 3 96 "$display", "[FAIL] READ addr=%h expected=%h got=%h", v0000026f26fd9a80_0, v0000026f26fd9b20_0, v0000026f26fd8220_0 {0 0 0};
    %load/vec4 v0000026f26fd8540_0;
    %addi 1, 0, 32;
    %store/vec4 v0000026f26fd8540_0, 0, 32;
T_0.3 ;
    %wait E_0000026f26f10a40;
    %end;
S_0000026f26ee2eb0 .scope task, "cpu_write_task" "cpu_write_task" 3 103, 3 103 0, S_0000026f26f779e0;
 .timescale -9 -12;
v0000026f26fd8180_0 .var "address", 31 0;
v0000026f26fd8f40_0 .var "data", 31 0;
TD_tb_direct_mapped_cache.cpu_write_task ;
    %wait E_0000026f26f10a40;
    %load/vec4 v0000026f26fd8180_0;
    %store/vec4 v0000026f26fd8ae0_0, 0, 32;
    %load/vec4 v0000026f26fd8f40_0;
    %store/vec4 v0000026f26fd8d60_0, 0, 32;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fd84a0_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fd9260_0, 0, 1;
    %wait E_0000026f26f10a40;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fd9260_0, 0, 1;
T_1.4 ;
    %load/vec4 v0000026f26fd8360_0;
    %pushi/vec4 1, 0, 1;
    %cmp/e;
    %flag_get/vec4 4;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_1.5, 6;
    %wait E_0000026f26f11400;
    %jmp T_1.4;
T_1.5 ;
    %vpi_call/w 3 118 "$display", "[WRITE COMPLETE] addr=%h data=%h", v0000026f26fd8180_0, v0000026f26fd8f40_0 {0 0 0};
    %wait E_0000026f26f10a40;
    %end;
    .scope S_0000026f26f42db0;
T_2 ;
    %wait E_0000026f26f117c0;
    %load/vec4 v0000026f26fcda10_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fccc50_0, 0, 32;
T_2.2 ;
    %load/vec4 v0000026f26fccc50_0;
    %cmpi/s 16, 0, 32;
    %jmp/0xz T_2.3, 5;
    %pushi/vec4 0, 0, 26;
    %ix/getv/s 3, v0000026f26fccc50_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fce230, 0, 4;
    %pushi/vec4 0, 0, 32;
    %ix/getv/s 3, v0000026f26fccc50_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fcdf10, 0, 4;
    %pushi/vec4 0, 0, 1;
    %ix/getv/s 3, v0000026f26fccc50_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fcc6b0, 0, 4;
    %pushi/vec4 0, 0, 1;
    %ix/getv/s 3, v0000026f26fccc50_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fcc890, 0, 4;
    %load/vec4 v0000026f26fccc50_0;
    %addi 1, 0, 32;
    %store/vec4 v0000026f26fccc50_0, 0, 32;
    %jmp T_2.2;
T_2.3 ;
    %jmp T_2.1;
T_2.0 ;
    %load/vec4 v0000026f26fcd8d0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.4, 8;
    %load/vec4 v0000026f26fcc610_0;
    %load/vec4 v0000026f26fcd970_0;
    %pad/u 6;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fce230, 0, 4;
    %load/vec4 v0000026f26fce0f0_0;
    %load/vec4 v0000026f26fcd970_0;
    %pad/u 6;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fcdf10, 0, 4;
    %load/vec4 v0000026f26fcccf0_0;
    %load/vec4 v0000026f26fcd970_0;
    %pad/u 6;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fcc6b0, 0, 4;
    %load/vec4 v0000026f26fcc570_0;
    %load/vec4 v0000026f26fcd970_0;
    %pad/u 6;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fcc890, 0, 4;
T_2.4 ;
T_2.1 ;
    %jmp T_2;
    .thread T_2;
    .scope S_0000026f26f4ef50;
T_3 ;
    %wait E_0000026f26f117c0;
    %load/vec4 v0000026f26fcd830_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26fcd150_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26fcdd30_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26fcdc90_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26f6e650_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6ebf0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6e790_0, 0;
    %pushi/vec4 0, 0, 26;
    %assign/vec4 v0000026f26f6ea10_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26f6f050_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6f0f0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6eab0_0, 0;
    %jmp T_3.1;
T_3.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6ebf0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6e790_0, 0;
    %load/vec4 v0000026f26fcc9d0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_3.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_3.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_3.4, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 3;
    %cmp/u;
    %jmp/1 T_3.5, 6;
    %dup/vec4;
    %pushi/vec4 4, 0, 3;
    %cmp/u;
    %jmp/1 T_3.6, 6;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
    %jmp T_3.8;
T_3.2 ;
    %load/vec4 v0000026f26f6e5b0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.9, 8;
    %load/vec4 v0000026f26f6e290_0;
    %assign/vec4 v0000026f26fcd150_0, 0;
    %load/vec4 v0000026f26f6e6f0_0;
    %assign/vec4 v0000026f26fcdd30_0, 0;
    %load/vec4 v0000026f26f6eb50_0;
    %assign/vec4 v0000026f26fcdc90_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
T_3.9 ;
    %jmp T_3.8;
T_3.3 ;
    %load/vec4 v0000026f26f6e830_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.11, 8;
    %load/vec4 v0000026f26fcdc90_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.13, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6e790_0, 0;
    %load/vec4 v0000026f26fccbb0_0;
    %assign/vec4 v0000026f26f6ea10_0, 0;
    %load/vec4 v0000026f26fcdd30_0;
    %assign/vec4 v0000026f26f6f050_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6f0f0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6eab0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6ebf0_0, 0;
    %jmp T_3.14;
T_3.13 ;
    %load/vec4 v0000026f26f6e1f0_0;
    %assign/vec4 v0000026f26f6e650_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6ebf0_0, 0;
T_3.14 ;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
    %jmp T_3.12;
T_3.11 ;
    %load/vec4 v0000026f26f6e470_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_3.17, 9;
    %load/vec4 v0000026f26f6e3d0_0;
    %and;
T_3.17;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.15, 8;
    %pushi/vec4 2, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
    %jmp T_3.16;
T_3.15 ;
    %pushi/vec4 3, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
T_3.16 ;
T_3.12 ;
    %jmp T_3.8;
T_3.4 ;
    %load/vec4 v0000026f26fcdfb0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.18, 8;
    %pushi/vec4 3, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
T_3.18 ;
    %jmp T_3.8;
T_3.5 ;
    %load/vec4 v0000026f26fcdfb0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.20, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6e790_0, 0;
    %load/vec4 v0000026f26fccbb0_0;
    %assign/vec4 v0000026f26f6ea10_0, 0;
    %load/vec4 v0000026f26fcd1f0_0;
    %assign/vec4 v0000026f26f6f050_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6f0f0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26f6eab0_0, 0;
    %load/vec4 v0000026f26fcdc90_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.22, 8;
    %load/vec4 v0000026f26fcd1f0_0;
    %assign/vec4 v0000026f26f6e650_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6ebf0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
    %jmp T_3.23;
T_3.22 ;
    %pushi/vec4 4, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
T_3.23 ;
T_3.20 ;
    %jmp T_3.8;
T_3.6 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6e790_0, 0;
    %load/vec4 v0000026f26fccbb0_0;
    %assign/vec4 v0000026f26f6ea10_0, 0;
    %load/vec4 v0000026f26fcdd30_0;
    %assign/vec4 v0000026f26f6f050_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6f0f0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6eab0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26f6ebf0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000026f26fcc9d0_0, 0;
    %jmp T_3.8;
T_3.8 ;
    %pop/vec4 1;
T_3.1 ;
    %jmp T_3;
    .thread T_3;
    .scope S_0000026f26f4ef50;
T_4 ;
    %wait E_0000026f26f0fa80;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fcd010_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fccf70_0, 0, 1;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fccb10_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fcc7f0_0, 0, 32;
    %load/vec4 v0000026f26fcc9d0_0;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_4.0, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 3;
    %cmp/u;
    %jmp/1 T_4.1, 6;
    %jmp T_4.2;
T_4.0 ;
    %load/vec4 v0000026f26fcdfb0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.3, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fcd010_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fccf70_0, 0, 1;
    %load/vec4 v0000026f26f6e8d0_0;
    %load/vec4 v0000026f26fcc930_0;
    %concat/vec4; draw_concat_vec4
    %concati/vec4 0, 0, 2;
    %store/vec4 v0000026f26fccb10_0, 0, 32;
    %load/vec4 v0000026f26f6e1f0_0;
    %store/vec4 v0000026f26fcc7f0_0, 0, 32;
T_4.3 ;
    %jmp T_4.2;
T_4.1 ;
    %load/vec4 v0000026f26fcdfb0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.5, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fcd010_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fccf70_0, 0, 1;
    %load/vec4 v0000026f26fccbb0_0;
    %load/vec4 v0000026f26fcc930_0;
    %concat/vec4; draw_concat_vec4
    %concati/vec4 0, 0, 2;
    %store/vec4 v0000026f26fccb10_0, 0, 32;
T_4.5 ;
    %jmp T_4.2;
T_4.2 ;
    %pop/vec4 1;
    %jmp T_4;
    .thread T_4, $push;
    .scope S_0000026f26f1c760;
T_5 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd8fe0_0, 0, 32;
T_5.0 ;
    %load/vec4 v0000026f26fd8fe0_0;
    %cmpi/s 256, 0, 32;
    %jmp/0xz T_5.1, 5;
    %pushi/vec4 268435456, 0, 32;
    %load/vec4 v0000026f26fd8fe0_0;
    %add;
    %ix/getv/s 4, v0000026f26fd8fe0_0;
    %store/vec4a v0000026f26fd9120, 4, 0;
    %load/vec4 v0000026f26fd8fe0_0;
    %addi 1, 0, 32;
    %store/vec4 v0000026f26fd8fe0_0, 0, 32;
    %jmp T_5.0;
T_5.1 ;
    %end;
    .thread T_5;
    .scope S_0000026f26f1c760;
T_6 ;
    %wait E_0000026f26f117c0;
    %load/vec4 v0000026f26fd99e0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26fd9ee0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26fd9440_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26fd8680_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26fd91c0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26fd9c60_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26fd9580_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000026f26fd9940_0, 0;
    %jmp T_6.1;
T_6.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26fd9440_0, 0;
    %load/vec4 v0000026f26fd9ee0_0;
    %nor/r;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_6.4, 9;
    %load/vec4 v0000026f26fd8c20_0;
    %and;
T_6.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.2, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26fd9ee0_0, 0;
    %load/vec4 v0000026f26fd9620_0;
    %assign/vec4 v0000026f26fd91c0_0, 0;
    %load/vec4 v0000026f26fd9f80_0;
    %assign/vec4 v0000026f26fd9c60_0, 0;
    %load/vec4 v0000026f26fd80e0_0;
    %assign/vec4 v0000026f26fd9580_0, 0;
    %pushi/vec4 3, 0, 32;
    %assign/vec4 v0000026f26fd9940_0, 0;
    %jmp T_6.3;
T_6.2 ;
    %load/vec4 v0000026f26fd9ee0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.5, 8;
    %load/vec4 v0000026f26fd9940_0;
    %cmpi/s 1, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_6.7, 5;
    %load/vec4 v0000026f26fd9940_0;
    %subi 1, 0, 32;
    %assign/vec4 v0000026f26fd9940_0, 0;
    %jmp T_6.8;
T_6.7 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000026f26fd9ee0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000026f26fd9440_0, 0;
    %load/vec4 v0000026f26fd91c0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.9, 8;
    %load/vec4 v0000026f26fd9580_0;
    %load/vec4 v0000026f26fd8400_0;
    %pad/u 10;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000026f26fd9120, 0, 4;
    %vpi_call/w 7 82 "$display", "[MEM WRITE] t=%0t addr=%h data=%h", $time, v0000026f26fd9c60_0, v0000026f26fd9580_0 {0 0 0};
    %jmp T_6.10;
T_6.9 ;
    %load/vec4 v0000026f26fd8400_0;
    %pad/u 10;
    %ix/vec4 4;
    %load/vec4a v0000026f26fd9120, 4;
    %assign/vec4 v0000026f26fd8680_0, 0;
    %load/vec4 v0000026f26fd8400_0;
    %pad/u 10;
    %ix/vec4 4;
    %load/vec4a v0000026f26fd9120, 4;
    %vpi_call/w 7 87 "$display", "[MEM READ] t=%0t addr=%h data=%h", $time, v0000026f26fd9c60_0, S<0,vec4,u32> {1 0 0};
T_6.10 ;
T_6.8 ;
T_6.5 ;
T_6.3 ;
T_6.1 ;
    %jmp T_6;
    .thread T_6;
    .scope S_0000026f26f779e0;
T_7 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fd8cc0_0, 0, 1;
T_7.0 ;
    %delay 5000, 0;
    %load/vec4 v0000026f26fd8cc0_0;
    %inv;
    %store/vec4 v0000026f26fd8cc0_0, 0, 1;
    %jmp T_7.0;
    %end;
    .thread T_7;
    .scope S_0000026f26f779e0;
T_8 ;
    %vpi_call/w 3 125 "$dumpfile", "cache.vcd" {0 0 0};
    %vpi_call/w 3 126 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000026f26f779e0 {0 0 0};
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026f26fdb130_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fd9260_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fd84a0_0, 0, 1;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd8ae0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd8d60_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fdb9f0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd8540_0, 0, 32;
    %pushi/vec4 4, 0, 32;
T_8.0 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_8.1, 5;
    %jmp/1 T_8.1, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0000026f26f117c0;
    %jmp T_8.0;
T_8.1 ;
    %pop/vec4 1;
    %wait E_0000026f26f10a40;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026f26fdb130_0, 0, 1;
    %vpi_call/w 3 141 "$display", "\012TEST 1: READ MISS" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd9a80_0, 0, 32;
    %pushi/vec4 268435456, 0, 32;
    %store/vec4 v0000026f26fd9b20_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_read, S_0000026f26ee2d20;
    %join;
    %vpi_call/w 3 144 "$display", "\012TEST 2: READ HIT" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd9a80_0, 0, 32;
    %pushi/vec4 268435456, 0, 32;
    %store/vec4 v0000026f26fd9b20_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_read, S_0000026f26ee2d20;
    %join;
    %vpi_call/w 3 147 "$display", "\012TEST 3: WRITE HIT" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd8180_0, 0, 32;
    %pushi/vec4 3735928559, 0, 32;
    %store/vec4 v0000026f26fd8f40_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_write_task, S_0000026f26ee2eb0;
    %join;
    %vpi_call/w 3 150 "$display", "\012TEST 4: READ DIRTY DATA" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd9a80_0, 0, 32;
    %pushi/vec4 3735928559, 0, 32;
    %store/vec4 v0000026f26fd9b20_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_read, S_0000026f26ee2d20;
    %join;
    %vpi_call/w 3 153 "$display", "\012TEST 5: DIRTY EVICTION" {0 0 0};
    %pushi/vec4 64, 0, 32;
    %store/vec4 v0000026f26fd9a80_0, 0, 32;
    %pushi/vec4 268435472, 0, 32;
    %store/vec4 v0000026f26fd9b20_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_read, S_0000026f26ee2d20;
    %join;
    %vpi_call/w 3 156 "$display", "\012TEST 6: VERIFY WRITE BACK" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000026f26fd9a80_0, 0, 32;
    %pushi/vec4 3735928559, 0, 32;
    %store/vec4 v0000026f26fd9b20_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_read, S_0000026f26ee2d20;
    %join;
    %vpi_call/w 3 159 "$display", "\012TEST 7: WRITE MISS" {0 0 0};
    %pushi/vec4 132, 0, 32;
    %store/vec4 v0000026f26fd8180_0, 0, 32;
    %pushi/vec4 3405691582, 0, 32;
    %store/vec4 v0000026f26fd8f40_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_write_task, S_0000026f26ee2eb0;
    %join;
    %vpi_call/w 3 162 "$display", "\012TEST 8: VERIFY WRITE ALLOCATE" {0 0 0};
    %pushi/vec4 132, 0, 32;
    %store/vec4 v0000026f26fd9a80_0, 0, 32;
    %pushi/vec4 3405691582, 0, 32;
    %store/vec4 v0000026f26fd9b20_0, 0, 32;
    %fork TD_tb_direct_mapped_cache.cpu_read, S_0000026f26ee2d20;
    %join;
    %vpi_call/w 3 165 "$display", "CACHE TEST SUMMARY" {0 0 0};
    %vpi_call/w 3 166 "$display", "PASS = %0d", v0000026f26fdb9f0_0 {0 0 0};
    %vpi_call/w 3 167 "$display", "FAIL = %0d", v0000026f26fd8540_0 {0 0 0};
    %load/vec4 v0000026f26fd8540_0;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_8.2, 4;
    %vpi_call/w 3 170 "$display", "ALL TESTS PASSED" {0 0 0};
    %jmp T_8.3;
T_8.2 ;
    %vpi_call/w 3 172 "$display", "CACHE TEST FAILED" {0 0 0};
T_8.3 ;
    %delay 20000, 0;
    %vpi_call/w 3 174 "$finish" {0 0 0};
    %end;
    .thread T_8;
    .scope S_0000026f26f779e0;
T_9 ;
    %delay 10000000, 0;
    %vpi_call/w 3 180 "$display", "[FATAL] Simulation timeout - possible deadlock" {0 0 0};
    %vpi_call/w 3 181 "$finish" {0 0 0};
    %end;
    .thread T_9;
# The file index is used to find the file name in the following table.
:file_names 8;
    "N/A";
    "<interactive>";
    "-";
    "tb_direct_mapped_cache.v";
    "direct_mapped_cache.v";
    "cache_controller.v";
    "cache_memory.v";
    "main_memory.v";