From ba350468ae20d79f7e2dddbf5343a629c0d60d40 Mon Sep 17 00:00:00 2001
From: Mohit Dsor <mohit.dsor@oss.qualcomm.com>
Date: Tue, 23 Jun 2026 17:59:49 +0530
Subject: [PATCH] PENDING: arm64: dts: qcom: Shikra LT9611UXD support

Device tree changes to support lt9611uxd hdmi-dsi driver.

Upstream-Status: Inappropriate [debug specific]
Signed-off-by: Mohit Dsor <mohit.dsor@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 127 ++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 98ab8380a317..5b0fef124559 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -96,6 +96,17 @@
 		};
 	};
 
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&lt9611_out>;
+			};
+		};
+	};
+
 	vreg_bt_3p3_dummy: regulator-bt-3p3-dummy {
 		compatible = "regulator-fixed";
 		regulator-name = "bt_3p3_dummy";
@@ -104,6 +115,25 @@
 		regulator-always-on;
 	};
 
+	vreg_lt9611_vcc: regulator-lt9611-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "lt9611_vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_reg_en>;
+	};
+
+	vreg_lt9611_vdd: regulator-lt9611-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "lt9611_vdd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
 	vreg_wlan_3p3_dummy: regulator-wlan-3p3-dummy {
 		compatible = "regulator-fixed";
 		regulator-name = "wlan_3p3_dummy";
@@ -333,6 +363,63 @@
 	};
 };
 
+&i2c4 {
+	status = "okay";
+
+	lt9611uxd: lt,lt9611uxd@41 {
+		compatible = "lontium,lt9611uxd";
+		reg = <0x41>;
+		interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>;
+		reset-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
+		vcc-supply = <&vreg_lt9611_vcc>;
+		vdd-supply = <&vreg_lt9611_vdd>;
+		lontium,port-select = <1>; /* PORT_SELECT_B */
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				lt9611_a: endpoint {
+					remote-endpoint = <&mdss_dsi0_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				lt9611_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&pm8150_l11>;
+	status = "okay";
+
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&lt9611_a>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	status = "okay";
+};
+
 &pcie {
 	wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
 
@@ -441,6 +528,22 @@
 	status = "okay";
 };
 
+&pm8150_gpios {
+	hdmi_reg_en: hdmi-reg-en-state {
+		pins = "gpio4";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		bias-disable;
+	};
+};
+
+
+&pm8150_l11 {
+        /* DSI VDDA - must be at NOM voltage for PHY PLL lock */
+        regulator-min-microvolt = <1232000>;
+        regulator-max-microvolt = <1232000>;
+        regulator-allow-set-load;
+};
+
 &q6apmbedai {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -595,6 +698,28 @@
 	};
 };
 
+&tlmm {
+	lt9611_irq_pin: lt9611-irq-state {
+		pins = "gpio85";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+		input-enable;
+	};
+
+	lt9611_rst_pin: lt9611-rst-state {
+		pins = "gpio76";
+		function = "gpio";
+		drive-strength = <8>;
+		output-high;
+		input-disable;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
 &uart8 {
 	status = "okay";
 
@@ -679,3 +804,5 @@
 		output-high;
 	};
 };
+
+