From e4de0fe861bddd7cbc857e0680e18a34d5f66448 Mon Sep 17 00:00:00 2001 From: bitglitcher <0xbitglitcher@gmail.com> Date: Wed, 8 Jul 2026 20:26:33 -0500 Subject: [PATCH 1/5] Update directions. --- README.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/README.md b/README.md index 5441872..3c017af 100644 --- a/README.md +++ b/README.md @@ -4,6 +4,30 @@ RISCV SoC Collab work. Join On [Discord](https://discord.gg/sQjhBvWXjF) if you interested in the project! +# *UPDATE* + +Team has decided to change course. Implementation of a simpler core will begin. +2 Cycle implementation in the works. RV32I. This is early development before we break +it down into a 5 stage pipeline. + + +--- + +## Simulation instructions + + +Setup environment variables. + +Run the following command inside the top directory of this project. +```sh +source setup.sh +``` + +Run make command in sim directory to build simulation. +```sh +make +``` + --- # General SoC Architecture idea From 61f24edbf6437eed2dde736912e6fbd73b36e67a Mon Sep 17 00:00:00 2001 From: bitglitcher <0xbitglitcher@gmail.com> Date: Wed, 8 Jul 2026 20:31:37 -0500 Subject: [PATCH 2/5] Add simple draft bash file to setup environment variables. --- setup.sh | 3 +++ 1 file changed, 3 insertions(+) create mode 100755 setup.sh diff --git a/setup.sh b/setup.sh new file mode 100755 index 0000000..90f3c43 --- /dev/null +++ b/setup.sh @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: MIT + +export CORE_REPO_PATH=$(pwd) From 0cf0633c9e76e49e1183f5e7050b992a6a086486 Mon Sep 17 00:00:00 2001 From: bitglitcher <0xbitglitcher@gmail.com> Date: Wed, 8 Jul 2026 20:32:52 -0500 Subject: [PATCH 3/5] Add simple Wishbone B4 compatible sram module. --- design/wb4_sram.sv | 86 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 design/wb4_sram.sv diff --git a/design/wb4_sram.sv b/design/wb4_sram.sv new file mode 100644 index 0000000..ade8211 --- /dev/null +++ b/design/wb4_sram.sv @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: MIT + +/* ------------------------------------------------------------------------- */ + + +`include "defaults/defaults.sv" + + +/* ------------------------------------------------------------------------- */ + + +/* + * Module: Internal SRAM With Wishbone BUS + * + * Parameters: + * num_words: Number of words in the memory (default = 4096). + * + */ +module sram #( + parameter num_words = 4096 +) ( + input logic clk, + input logic rst, + + // Wishbone signals + input logic [31:0] addr_i, + input logic [31:0] dat_i, + output logic [31:0] dat_o, + + output logic ack_o, + output logic err_o, + input logic cyc_i, + input logic stb_i, + input logic we_i +); + reg [31:0] memory [0:(num_words - 1)]; + + // For address calculation + localparam ADDR_WIDTH = $clog2(num_words); + logic [ADDR_WIDTH-1:0] word_addr; + logic addr_valid; + + assign word_addr = addr_i[ADDR_WIDTH+1:2]; // Byte to word address + assign addr_valid = (addr_i[31:ADDR_WIDTH+2] == 0); // Check upper bits are 0 + + always @(posedge clk) begin + if (rst) + begin + ack_o <= 1'b0; + err_o <= 1'b0; + dat_o <= 32'b0; + end + else + begin + if (cyc_i && stb_i) begin + if (addr_valid) begin + if (we_i) + begin + memory[word_addr] <= dat_i; + end + else + begin + dat_o <= memory[word_addr]; + end + ack_o <= 1'b1; + err_o <= 1'b0; + end + else + begin + ack_o <= 1'b0; + err_o <= 1'b1; + end + end + else + begin + ack_o <= 1'b0; + err_o <= 1'b0; + end + end + end +endmodule + +/* ------------------------------------------------------------------------- */ + + +/* End of file. */ From 7acb9eaf126ad72057feedbebc23d6397cde4cc5 Mon Sep 17 00:00:00 2001 From: bitglitcher <0xbitglitcher@gmail.com> Date: Wed, 8 Jul 2026 20:36:25 -0500 Subject: [PATCH 4/5] Add simple draft structure for the RV32I Core. --- design/core.sv | 72 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 64 insertions(+), 8 deletions(-) diff --git a/design/core.sv b/design/core.sv index eab3119..22fa5b8 100644 --- a/design/core.sv +++ b/design/core.sv @@ -1,13 +1,69 @@ `include "core.pkg" module core - ( - input clk, - input rst - ); - - - - +( + //Clock is shared with WB4 BUS + input logic clk, + input logic rst, + + + //Wishbone signals + output logic [31:0] addr_o, + input logic [31:0] dat_i, + output logic [31:0] dat_o, + + input logic ack_i, + input logic err_i, + output logic cyc_o, + output logic stb_o, + output logic we_o + +); +typedef enum logic [0:1] { FETCH, EXECUTE } exec_state; + +exec_state current_state = FETCH; + +logic [31:0] IR = 0; + +wire [6:0] funct7 = IR[31:25]; +wire [4:0] rs2 = IR[24:20]; +wire [4:0] rs1 = IR[19:15]; +wire [2:0] funct3 = IR[14:12]; +wire [4:0] rd = IR[11:7]; +wire [6:0] opcode = IR[6:0]; + +wire [11:0] imm = IR[31:20]; + +wire [6:0] imm_11_5 = IR[31:25]; +wire [4:0] imm_4_0 = IR[11:7]; + +wire [19:0] imm_31_12 = IR[31:12]; + +//Main state machine for the instruction execution cycle. +always@(posedge clk) +begin + case (current_state) + FETCH:; + //TODO: Implement Fetch From Wishbone 4 interface. Synchronous Mode. + //Illustration 4-2: WISHBONE Classic synchronous cycle terminated burst + //https://cdn.opencores.org/downloads/wbspec_b4.pdf + //Page: 66 + + EXECUTE:; + //TODO: Implement ALU Execution + + //TODO: Implement Memory Write + + //TODO: Implement Memory Reads + + //TODO: Implement Branch Instructions + + //NOTES: The state machine can have nested states to accommodate wishbone BUS logic. + + default:; + endcase +end + + endmodule From 2b19857373041a561dc73a25a673ddbc50cd3379 Mon Sep 17 00:00:00 2001 From: bitglitcher <0xbitglitcher@gmail.com> Date: Wed, 15 Jul 2026 23:51:38 -0500 Subject: [PATCH 5/5] Basic running simulation. --- .gitignore | 1 + Makefile | 0 design/core.sv | 8 ++-- design/soc.sv | 0 design/wb4_sram.sv | 13 +++++-- firmware/Makefile | 7 ++++ firmware/crt0.s | 13 +++++++ sim/Makefile | 33 +++++----------- testbench/tb.sv | 97 ++++++++++++++++++++-------------------------- 9 files changed, 85 insertions(+), 87 deletions(-) create mode 100644 Makefile create mode 100644 design/soc.sv create mode 100644 firmware/Makefile create mode 100644 firmware/crt0.s diff --git a/.gitignore b/.gitignore index e8b9d4a..2382745 100644 --- a/.gitignore +++ b/.gitignore @@ -53,3 +53,4 @@ dkms.conf #Iverilog Simulation Files *.vcd +*a.out \ No newline at end of file diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..e69de29 diff --git a/design/core.sv b/design/core.sv index 22fa5b8..c886d81 100644 --- a/design/core.sv +++ b/design/core.sv @@ -1,5 +1,3 @@ -`include "core.pkg" - module core ( //Clock is shared with WB4 BUS @@ -20,11 +18,11 @@ module core ); -typedef enum logic [0:1] { FETCH, EXECUTE } exec_state; +typedef enum logic [1:0] { FETCH, EXECUTE } exec_state_t; -exec_state current_state = FETCH; +exec_state_t current_state = FETCH; -logic [31:0] IR = 0; +logic [64:0] IR = 0; wire [6:0] funct7 = IR[31:25]; wire [4:0] rs2 = IR[24:20]; diff --git a/design/soc.sv b/design/soc.sv new file mode 100644 index 0000000..e69de29 diff --git a/design/wb4_sram.sv b/design/wb4_sram.sv index ade8211..57a1046 100644 --- a/design/wb4_sram.sv +++ b/design/wb4_sram.sv @@ -3,7 +3,8 @@ /* ------------------------------------------------------------------------- */ -`include "defaults/defaults.sv" +//TODO: Will need to redo defaults. +// `include "defaults/defaults.sv" /* ------------------------------------------------------------------------- */ @@ -16,7 +17,7 @@ * num_words: Number of words in the memory (default = 4096). * */ -module sram #( +module wb4_sram #( parameter num_words = 4096 ) ( input logic clk, @@ -37,8 +38,12 @@ module sram #( // For address calculation localparam ADDR_WIDTH = $clog2(num_words); - logic [ADDR_WIDTH-1:0] word_addr; - logic addr_valid; + wire [ADDR_WIDTH-1:0] word_addr; + wire addr_valid; + + initial begin + $readmemh("../firmware/crt0.hex", memory); + end assign word_addr = addr_i[ADDR_WIDTH+1:2]; // Byte to word address assign addr_valid = (addr_i[31:ADDR_WIDTH+2] == 0); // Check upper bits are 0 diff --git a/firmware/Makefile b/firmware/Makefile new file mode 100644 index 0000000..ea66c01 --- /dev/null +++ b/firmware/Makefile @@ -0,0 +1,7 @@ + + +all: + riscv64-unknown-elf-as -march=rv64i -mabi=lp64 crt0.s -o crt0.o + riscv64-unknown-elf-ld -Ttext=0x0 -o crt0.elf crt0.o + riscv64-unknown-elf-objdump -d crt0.elf + riscv64-unknown-elf-objcopy -O verilog --verilog-data-width=4 crt0.elf crt0.hex diff --git a/firmware/crt0.s b/firmware/crt0.s new file mode 100644 index 0000000..5e6b653 --- /dev/null +++ b/firmware/crt0.s @@ -0,0 +1,13 @@ + .section .text + .globl _start + +_start: + addi x1, x0, 5 # x1 = 5 + addi x2, x0, 3 # x2 = 3 + add x3, x1, x2 # x3 = 8 + sd x3, 0(x0) # mem[0] = 8 + li x4, 4 # x4 = 4 +loop: + addi x4, x4, -1 # x4-- + bnez x4, loop # branch until x4 == 0 + ebreak # done \ No newline at end of file diff --git a/sim/Makefile b/sim/Makefile index 60e7d9c..6661388 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,31 +1,16 @@ -TOPFILE ?= $(CORE_REPO_PATH)/sim/top.sv -DSFILE ?= $(CORE_REPO_PATH)/design/core.sv -TBFILE ?= $(CORE_REPO_PATH)/testbench/tb.sv -all: - iverilog \ - -g 2012 \ - -g relative-include \ - -c $(CORE_REPO_PATH)/sim/top.filelist \ - $(TOPFILE); - ./a.out; -core: - iverilog \ - -g 2012 \ - -g relative-include \ - -c $(CORE_REPO_PATH)/design/core.filelist \ - $(DSFILE); - ./a.out; +############# -tb: - iverilog \ - -g 2012 \ - -g relative-include \ - -c $(CORE_REPO_PATH)/testbench/tb.filelist \ - $(TBFILE); - ./a.out; +DESIGN = ../design +TESTBENCH = ../testbench +RTL_FILES = $(DESIGN)/wb4_sram.sv $(DESIGN)/core.sv + +SOC_TEST_BENCH = $(RTL_FILES) $(TESTBENCH)/tb.sv + +all: $(SOC_TEST_BENCH) + iverilog $(SOC_TEST_BENCH) -g2012 clean: rm -rf *.out *.vcd *.log; \ No newline at end of file diff --git a/testbench/tb.sv b/testbench/tb.sv index 9733bd2..4182e68 100644 --- a/testbench/tb.sv +++ b/testbench/tb.sv @@ -1,28 +1,23 @@ -`include "tb.pkg" +`timescale 1ps/1ps -module tb -( - `ifndef __sim__ - input logic clk, - input logic rst - `endif -); + +module tb(); //Internal RAM for BOOT ROM parameter SDRAM_LENGHT = 4096; //Wishobne interface -logic [31:0] ADR_O; -logic [31:0] DAT_O; -logic [31:0] DAT_I; -logic WE_O; -logic STB_O; -logic ACK_I; -logic CYC_O; -logic ERR_I; -logic RTY_I; -logic [2:0] CTI_O; -logic STALL_I; +logic [31:0] wb_addr; +logic [31:0] wb_dat_i; //Master Side naming. +logic [31:0] wb_dat_o; //Master Side naming. +logic wb_ack; +logic wb_err; +logic wb_cyc; +logic wb_stb; +logic wb_we; + + +logic rst; //Generated clock signal for out simulation logic clk_gen = 0; @@ -34,11 +29,6 @@ begin rst_gen = ~rst; end - -`ifdef __sim__ - -logic clk; -logic rst; initial begin $dumpfile("tb.vcd"); $dumpvars(0,tb); @@ -65,40 +55,39 @@ initial begin end end end -`endif -wb_test_master wb_test_master_0 + +core core0 ( - .WB_CLK_I(clk_gen), - .WB_RST_I(rst_gen), - .WB_ADR_O(ADR_O), - .WB_DAT_O(DAT_O), - .WB_DAT_I(DAT_I), - .WB_WE_O(WE_O), - .WB_STB_O(STB_O), - .WB_ACK_I(ACK_I), - .WB_CYC_O(CYC_O), - .WB_ERR_I(ERR_I), - .WB_RTY_I(RTY_I), - .WB_CTI_O(CTI_O), - .WB_STALL_I(STALL_I) + //Clock is shared with WB4 BUS + .clk(clk_gen), + .rst(rst_gen), + + //Wishbone signals + .addr_o(wb_addr), + .dat_i(wb_dat_i), + .dat_o(wb_dat_o), + + .ack_i(wb_ack), + .err_i(wb_err), + .cyc_o(wb_cyc), + .stb_o(wb_stb), + .we_o(wb_we) + ); -ram ram_0 -( - .WB_CLK_I(clk_gen), - .WB_RST_I(rst_gen), - .WB_ADR_I(ADR_O), - .WB_DAT_O(DAT_I), - .WB_DAT_I(DAT_O), - .WB_WE_I(WE_O), - .WB_STB_I(STB_O), - .WB_ACK_O(ACK_I), - .WB_CYC_I(CYC_O), - .WB_ERR_O(ERR_I), - .WB_RTY_O(RTY_I), - .WB_CTI_I(CTI_O), - .WB_STALL_O(STALL_I) +wb4_sram sram0 ( + .clk(clk_gen), + .rst(rst_gen), + // Wishbone signals + .addr_i(wb_addr), + .dat_i(wb_dat), + .dat_o(wb_dat), + .ack_o(wb_ack), + .err_o(wb_err), + .cyc_i(wb_cyc), + .stb_i(wb_stb), + .we_i(wb_we) );