Skip to content
View Nishmitha07's full-sized avatar
  • Udupi, Karnataka, India

Block or report Nishmitha07

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Nishmitha07/README.md

Hi there 👋 I'm Nishmitha

🎓 Electronics & Communication Engineering Student

I enjoy building practical engineering solutions using Embedded Systems, IoT, VLSI, and Web Development.

🛠️ Skills

  • Verilog
  • Arduino
  • ESP32
  • MATLAB
  • C
  • C++
  • Python
  • HTML
  • CSS
  • JavaScript

🚀 Projects

  • 🌱 Smart Compost Bin
  • 🐶 Automatic Pet Feeder
  • ⚡ RISC-V Clock Gating
  • 🍲 Recipe Finder
  • 🌦️ Weather App
  • 💰 Budget Tracker
  • 🛍️ Product Landing Page
  • 🎨 Educare UI (Figma)
  • 💼 Portfolio Website

🌱 Currently Learning

  • FPGA Design
  • Embedded Systems
  • VLSI

📫 Connect with Me

Pinned Loading

  1. smart-compost-bin smart-compost-bin Public

    An IoT-based smart compost bin using ESP32, sensors, and automation for efficient compost management.

    C++

  2. automatic-pet-feeder automatic-pet-feeder Public

    An IoT-based Automatic Pet Feeder using Arduino/ESP32 for scheduled and remote pet feeding.

    C++

  3. educare-digital-learning-platform educare-digital-learning-platform Public

    First Prize winning design thinking project focused on improving education in government schools through an innovative digital learning platform.

  4. nb-arts-landing-page nb-arts-landing-page Public

    A responsive handcrafted products landing page for NB ARTS built using HTML and CSS featuring product showcases, navigation menus, and a modern user interface.

    CSS

  5. rv32i-clock-gating rv32i-clock-gating Public

    Instruction-Aware Fine-Grained Clock Gating in an Open Source RV32I Processor using Verilog HDL.

    Verilog