[svdconv] Generate position/mask macros for dim fields

.github/workflows/cpp-linter.yml

@@ -54,7 +54,7 @@ jobs:
           --platform=unix64 --std=c++17 --verbose --std=c++17 \
           -i./tools/buildmgr/test -i./tools/packchk/test \
           -i./tools/packgen/test -i./tools/projmgr/test \
-          -i./tools/svdconv/Test -i./test \
+          -i./tools/svdconv/test -i./test \
           --template="|{file}|{line}|{severity}|{message}|" \
           --output-file=./${{ env.linter_report }} .
 

tools/svdconv/CMakeLists.txt

@@ -13,6 +13,6 @@ add_subdirectory(SVDModel)
 add_subdirectory(SVDGenerator)
 add_subdirectory(SVDConv)
 
-add_subdirectory(Test/data)
-add_subdirectory(Test/UnitTests)
-add_subdirectory(Test/integtests)
+add_subdirectory(test/data)
+add_subdirectory(test/unittests)
+add_subdirectory(test/integtests)

tools/svdconv/SVDConv/cmdFile.cf.in

@@ -1,4 +1,4 @@
-"@CMAKE_CURRENT_SOURCE_DIR@/../Test/SDCMSIS-1369/test.svd"
+"@CMAKE_CURRENT_SOURCE_DIR@/../test/SDCMSIS-1369/test.svd"
 -o "@CMAKE_CURRENT_BINARY_DIR@/Output"
 -b "@CMAKE_CURRENT_BINARY_DIR@/Output/error.log"
 --create-folder

tools/svdconv/SVDGenerator/src/HeaderData_PosMask.cpp

@@ -183,6 +183,23 @@ bool HeaderData::CreateRegisterPosMask(SvdRegister* reg, PosMaskNames *posMaskNa
       continue;
     }
 
+    const auto dim = field->GetDimension();
+    if(dim) {
+      const auto expr = dim->GetExpression();
+      if(expr && expr->GetType() == SvdTypes::Expression::EXTEND) {
+        const auto& dimChilds = dim->GetChildren();
+        for(const auto dimChild : dimChilds) {
+          const auto dimField = dynamic_cast<SvdField*>(dimChild);
+          if(!dimField || !dimField->IsValid()) {
+            continue;
+          }
+
+          CreateFieldPosMask(dimField, posMaskNames);
+        }
+        continue;
+      }
+    }
+
     CreateFieldPosMask(field, posMaskNames);
   }
 

tools/svdconv/jenkins/pipeline.groovy

@@ -12,7 +12,7 @@ def baseFolderWin       = baseFolder.replaceAll('/', '\\\\')
 def buildFolder         = 'build'
 def target              = "SVDConv"
 def unittest            = "SVDConvUnitTests"
-def unittestFolder      = "tools/svdconv/Test/UnitTests"
+def unittestFolder      = "tools/svdconv/test/unittests"
 def unittestFolderWin   = unittestFolder.replaceAll('/', '\\\\')
 
 // pipeline controlling variables

tools/svdconv/test/data/posMaskDim/PosMaskDim.svd

@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>ARM Ltd.</vendor>
+  <vendorID>ARM</vendorID>
+  <name>PosMaskDim</name>
+  <series>ARM Cortex M3</series>
+  <version>1.0</version>
+  <description>Test device for dim fields in pos/mask generation.</description>
+
+  <cpu>
+    <name>CM3</name>
+    <revision>r2p1</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+
+  <peripherals>
+    <peripheral>
+      <name>TIM</name>
+      <description>Timer.</description>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA[%s]</name>
+          <description>Data register.</description>
+          <addressOffset>0x0</addressOffset>
+          <dim>256</dim>
+          <dimIncrement>4</dimIncrement>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>PIN%s</name>
+              <description>Pin data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <dim>8</dim>
+              <dimIncrement>1</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Channel disabled.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enabled</name>
+                  <description>Channel enabled.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>

tools/svdconv/Test/integtests/src/SvdConvIntegTests.cpp → tools/svdconv/test/integtests/src/SvdConvIntegTests.cpp

@@ -13,6 +13,7 @@
 #include <list>
 #include <fstream>
 #include <regex>
+#include <vector>
 
 using namespace std;
 using namespace testing;
@@ -203,3 +204,51 @@ TEST_F(SvdConvIntegTests, CheckResetMask) {
   }
 }
 
+TEST_F(SvdConvIntegTests, CheckPosMaskDimFields) {
+  const string& inFile = SvdConvIntegTestEnv::localtestdata_dir + "/posMaskDim/PosMaskDim.svd";
+  const string testOut = SvdConvIntegTestEnv::testoutput_dir + "/posMaskDim";
+  ASSERT_TRUE(RteFsUtils::Exists(inFile));
+
+  Arguments args("SVDConv.exe", inFile);
+  args.add({ "-o", testOut, "--generate=header", "--fields=macro", "--create-folder" });
+
+  SvdConv svdConv;
+  EXPECT_EQ(0, svdConv.Check(args, args, nullptr));
+
+  const string testOutHeader = testOut + "/PosMaskDim.h";
+  ASSERT_TRUE(RteFsUtils::Exists(testOutHeader));
+
+  string buf;
+  RteFsUtils::ReadFile(testOutHeader, buf);
+  ASSERT_FALSE(buf.empty());
+
+  const vector<pair<string, string>> expectedMacros = {
+    { "#define TIM_DATA_PIN0_Pos", "(0UL)" },
+    { "#define TIM_DATA_PIN0_Msk", "(0x1UL)" },
+    { "#define TIM_DATA_PIN1_Pos", "(1UL)" },
+    { "#define TIM_DATA_PIN1_Msk", "(0x2UL)" },
+    { "#define TIM_DATA_PIN2_Pos", "(2UL)" },
+    { "#define TIM_DATA_PIN2_Msk", "(0x4UL)" },
+    { "#define TIM_DATA_PIN3_Pos", "(3UL)" },
+    { "#define TIM_DATA_PIN3_Msk", "(0x8UL)" },
+    { "#define TIM_DATA_PIN4_Pos", "(4UL)" },
+    { "#define TIM_DATA_PIN4_Msk", "(0x10UL)" },
+    { "#define TIM_DATA_PIN5_Pos", "(5UL)" },
+    { "#define TIM_DATA_PIN5_Msk", "(0x20UL)" },
+    { "#define TIM_DATA_PIN6_Pos", "(6UL)" },
+    { "#define TIM_DATA_PIN6_Msk", "(0x40UL)" },
+    { "#define TIM_DATA_PIN7_Pos", "(7UL)" },
+    { "#define TIM_DATA_PIN7_Msk", "(0x80UL)" },
+  };
+  for(const auto& [name, value] : expectedMacros) {
+    const auto namePos = buf.find(name);
+    ASSERT_NE(string::npos, namePos) << name;
+    const auto lineEnd = buf.find('\n', namePos);
+    const auto valuePos = buf.find(value, namePos);
+    ASSERT_NE(string::npos, valuePos) << name;
+    EXPECT_LT(valuePos, lineEnd) << name;
+  }
+
+  EXPECT_EQ(string::npos, buf.find("#define TIM_DATA_PIN_Pos"));
+  EXPECT_EQ(string::npos, buf.find("#define TIM_DATA_PIN_Msk"));
+}

tools/svdconv/Test/UnitTests/CMakeLists.txt → tools/svdconv/test/unittests/CMakeLists.txt

@@ -13,7 +13,7 @@ set_property(TARGET SVDConvUnitTests PROPERTY
 set_property(TARGET SVDConvUnitTests PROPERTY
   VS_DEBUGGER_WORKING_DIRECTORY ${CMAKE_BINARY_DIR})
 
-target_link_libraries(SVDConvUnitTests PUBLIC SVDModel SVDGenerator gtest_main)
+target_link_libraries(SVDConvUnitTests PUBLIC svdconvlib gtest_main)
 
 add_test(NAME SVDConvUnitTests
          COMMAND SVDConvUnitTests --gtest_output=xml:test_reports/svdconvunittests-report-${SYSTEM}-${CPU_ARCH}$<$<BOOL:${COVERAGE}>:_cov>.xml

tools/svdconv/test/unittests/src/GeneratorTest.cpp

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2010-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "CodeGenerator.h"
+#include "HeaderData.h"
+#include "SvdDimension.h"
+#include "SvdField.h"
+#include "SvdRegister.h"
+
+#include "gtest/gtest.h"
+#include <memory>
+#include <string>
+
+using namespace std;
+
+
+TEST(CodeGenerator, Check) {
+#if 0
+  CodeGenerator gen;
+  const string text = "This is a %i printf %s";
+  int num = 42;
+  const char* textInsert = "insertion test";
+
+  const string& res = gen.FormatStr(text, num, textInsert);
+
+  ASSERT_EQ("This is a 42 printf insertion test", res);
+#endif
+}
+
+
+namespace {
+
+class RootItem : public SvdItem {
+public:
+  RootItem() : SvdItem(nullptr) {}
+
+  const string& GetPrependToName() override { return m_empty; }
+  const string& GetAppendToName() override { return m_empty; }
+
+private:
+  const string m_empty;
+};
+
+class TestHeaderData : public HeaderData {
+public:
+  using HeaderData::HeaderData;
+  using HeaderData::CreateRegisterPosMask;
+};
+
+SvdField* AddField(SvdItem* parent, const string& name, uint32_t offset) {
+  const auto field = new SvdField(parent);
+  field->SetName(name);
+  field->SetOffset(offset);
+  field->SetBitWidth(1);
+  parent->AddItem(field);
+  return field;
+}
+
+} // namespace
+
+
+TEST(HeaderData, CreateRegisterPosMaskHandlesDimensionVariants) {
+  SvdOptions options;
+  FileHeaderInfo fileHeaderInfo;
+  TestHeaderData headerData(fileHeaderInfo, options);
+
+  auto root = make_unique<RootItem>();
+  const auto reg = new SvdRegister(root.get());
+  reg->SetName("CTRL");
+  root->AddItem(reg);
+
+  const auto fields = new SvdFieldContainer(reg);
+  reg->AddItem(fields);
+  AddField(fields, "PLAIN", 0);
+
+  const auto arrayField = AddField(fields, "ARRAY", 1);
+  const auto arrayDim = new SvdDimension(arrayField);
+  arrayDim->GetExpression()->SetType(SvdTypes::Expression::ARRAY);
+  arrayField->SetDimension(arrayDim);
+
+  const auto extendField = AddField(fields, "EXTEND%s", 2);
+  const auto extendDim = new SvdDimension(extendField);
+  extendDim->GetExpression()->SetType(SvdTypes::Expression::EXTEND);
+  extendField->SetDimension(extendDim);
+
+  AddField(extendDim, "EXTEND0", 2);
+  const auto invalidField = AddField(extendDim, "EXTEND1", 3);
+  invalidField->SetValid(false);
+  extendDim->AddItem(new SvdItem(extendDim));
+
+  PosMaskNames names;
+  names.name = "TEST";
+  EXPECT_TRUE(headerData.CreateRegisterPosMask(reg, &names));
+}
+
+
+