XiangShan
Open-source high-performance RISC-V processor
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- XiangShanLab Public
A learning and practice repository for the open-source XiangShan RISC-V processor, featuring a full pathway from environment setup to microarchitecture optimization, designed for developers, students, and researchers.
OpenXiangShan/XiangShanLab’s past year of commit activity - XSCache Public
Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.
OpenXiangShan/XSCache’s past year of commit activity - ZhuJiang Public
OpenXiangShan/ZhuJiang’s past year of commit activity - HBL2 Public Forked from OpenXiangShan/CoupledL2
Open-source non-blocking L2 cache, used in XS-AI system
OpenXiangShan/HBL2’s past year of commit activity
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