Fix/mxfp4 a4w4 bm16 streaming accuracy#3
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The FlyDSL gemm2 a4w4 port lost accuracy on the BM16 (M<=128) streaming K-loop for K_TILES_TOTAL==8 (D_INTER=2048, e.g. dsv3_a): the triple-buffered (3-slot) A->LDS pipeline did not reliably drain the async raw.ptr.buffer.load.lds of a streamed slot before that slot's ds_read 3 iterations later, producing non-deterministic garbage (e2e logits_diff ~0.02-0.05 vs the ~0.009 fp4 floor; cosine ~0.90). Other K_TILES (4/6/10/12) happened to schedule cleanly at 3 slots. - Widen the streaming A-slot buffer from 3 to 4 (quad buffer): adds slack between a slot's read and its next overwrite, hiding the load latency and making all K_TILES_TOTAL deterministic. LDS cost is free -- the s_Aq slots stay <= the lds_acc cshuffle union they overlap, so per-WG LDS is unchanged. - Gate the streaming issue_a_load_lds on wave < n_load_waves (matching the prologue): at BM16 only waves 0,1 hold A rows; ungated, waves 2,3 streamed into lds_row 16/24 (past the BM16 slot) from the next m-block's rows. Verified: dsv3_a / dsv4_ep8 / kimi / dsv3_b / minimax_a / dsv4_tp2 all at the ~0.009 fp4 floor and deterministic across runs; large-M (BM32/BM128) unchanged; 33 standalone gemm1/gemm2 port tests pass. Co-Authored-By: Claude Opus 4 (1M context) <noreply@anthropic.com>
gemm_moe_tune.py's run_config benchmarked a4w4 (fp4 act + fp4 weight) with the wrong weight layout and gate_mode, so its accuracy check reported garbage (err_ratio ~1.0, 99.7% elements off) for every a4w4 shape -- the same class of bug already fixed in op_tests/test_moe_2stage.py (commit 6a580ab) but missed in the tuner. - include fp4x2 activations in the a16w4 shuffle branch so a4w4 gets shuffle_weight_a16w4 / shuffle_scale_a16w4 like a16w4/a8w4 (the FlyDSL port the a4w4 MoE runs on expects the gate-up-interleaved a16w4 layout). - pass gate_mode=interleave to fused_moe for mxfp4 weights (a4w4/a8w4/a16w4) and mxfp8, mirroring op_tests _effective_gate_mode (the a4w4 tuned rows are interleave-keyed; the default SEPARATED reaches the wrong dispatch). - add the top-level GateMode import the new code needs. Co-Authored-By: Claude Opus 4 (1M context) <noreply@anthropic.com>
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