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fix(linker): correct several cross-toolchain memory map inconsistencies #113

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2 changes: 1 addition & 1 deletion .../B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
2 changes: 1 addition & 1 deletion ...M-SUBG1/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
2 changes: 1 addition & 1 deletion ...cts/B-WL5M-SUBG1/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl5mxx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
2 changes: 1 addition & 1 deletion .../Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl5mxx_flash_cm0plus.icf
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08020000;
/*-Memory Regions-*/
/***** FLASH part dedicated to M0+ *****/
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803EFFF;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
/***** SRAM2 shared allocated by M0+ *****/
define symbol __ICFEDIT_region_RAM2_SHARED_start__ = 0x20009000;
define symbol __ICFEDIT_region_RAM2_SHARED_end__ = 0x20009FFF;
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2 changes: 1 addition & 1 deletion ...ts/B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/EWARM/stm32wl5mxx_flash_cm4.icf
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/***** Backup SRAM2 dedicated to M4 *****/
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x4000; /*0x400;*/
Expand Down
2 changes: 1 addition & 1 deletion .../B-WL5M-SUBG1/Demonstrations/LocalNetwork_Sensor/Sensor/MDK-ARM/stm32wl5mxx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x0000C000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
6 changes: 3 additions & 3 deletions Projects/B-WL5M-SUBG1/Templates/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
/***** FLASH part dedicated to M4 *****/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
/***** Non-backup SRAM1 dedicated to M4 *****/
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/***** Backup SRAM2 dedicated to M4 *****/
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
Expand Down
8 changes: 4 additions & 4 deletions Projects/B-WL5M-SUBG1/Templates/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -2,18 +2,18 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************

LR_IROM1 0x08000000 0x00020000 { ; load region size_region
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
; FLASH part dedicated to M4
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Non-backup SRAM1 dedicated to M4
RW_IRAM1 0x20000000 0x00004000 { ; RW data
RW_IRAM1 0x20000000 0x00008000 { ; RW data
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
6 changes: 3 additions & 3 deletions Projects/B-WL5M-SUBG1/Templates/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Memories definition */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */
}

/* Sections */
Expand Down
6 changes: 3 additions & 3 deletions Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/EWARM/stm32wl5mxx_flash_cm4.icf
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
/***** FLASH part dedicated to M4 *****/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
/***** Non-backup SRAM1 dedicated to M4 *****/
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/***** Backup SRAM2 dedicated to M4 *****/
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
Expand Down
8 changes: 4 additions & 4 deletions Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/MDK-ARM/stm32wl5mxx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -2,18 +2,18 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************

LR_IROM1 0x08000000 0x00020000 { ; load region size_region
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
; FLASH part dedicated to M4
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Non-backup SRAM1 dedicated to M4
RW_IRAM1 0x20000000 0x00004000 { ; RW data
RW_IRAM1 0x20000000 0x00008000 { ; RW data
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
6 changes: 3 additions & 3 deletions Projects/B-WL5M-SUBG1/Templates_LL/SingleCore/STM32CubeIDE/STM32WL5MOCHX_FLASH.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Memories definition */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */
}

/* Sections */
Expand Down
2 changes: 1 addition & 1 deletion ...NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
2 changes: 1 addition & 1 deletion ...-WL55JC/Applications/LoRaWAN/LoRaWAN_End_Node_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
2 changes: 1 addition & 1 deletion ...ts/NUCLEO-WL55JC/Applications/LoRaWAN/LoRaWAN_Relay_LBM/MDK-ARM/stm32wl55xx_flash_cm4.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,6 @@ LR_IROM1 0x08000000 0x00040000 { ; load region size_region
.ANY (+RW +ZI)
}
; Backup SRAM2 dedicated to M4
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
RW_IRAM2 0x20009000 EMPTY 0x00007000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
}
}
2 changes: 1 addition & 1 deletion .../Applications/SubGHz_Phy/SubGHz_Phy_PingPong_DualCore/EWARM/stm32wl55xx_flash_cm0plus.icf
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08020000;
/*-Memory Regions-*/
/***** FLASH part dedicated to M0+ *****/
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803EFFF;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
/***** SRAM2 shared allocated by M0+ *****/
define symbol __ICFEDIT_region_RAM2_SHARED_start__ = 0x20009000;
define symbol __ICFEDIT_region_RAM2_SHARED_end__ = 0x20009FFF;
Expand Down
11 changes: 5 additions & 6 deletions Projects/NUCLEO-WL55JC/Examples/CORTEX/CORTEXM_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
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Expand Up @@ -14,10 +14,9 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Memories definition */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */
RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 16K
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */
}

/* Sections */
Expand Down Expand Up @@ -118,10 +117,10 @@ SECTIONS

} >RAM1 AT> ROM

.ROarraySection (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
.ROarraySection 0x20002000 (READONLY) : /* fixed address: matches ARRAY_ADDRESS_START in stm32_mpu.c and the IAR #pragma location. The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
*(.ROarraySection*)
} >RAM
} >RAM1

/* Uninitialized data section into "SRAM1" Ram type memory */
. = ALIGN(8);
Expand Down
7 changes: 3 additions & 4 deletions Projects/NUCLEO-WL55JC/Examples_LL/CORTEX/CORTEX_MPU/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
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Expand Up @@ -15,8 +15,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */
RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 16K
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 */
}

Expand Down Expand Up @@ -118,10 +117,10 @@ SECTIONS

} >RAM1 AT> ROM

.ROarraySection (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
.ROarraySection 0x20002000 (READONLY) : /* fixed address: matches ARRAY_ADDRESS_START in main.c and the IAR #pragma location. The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
*(.ROarraySection*)
} >RAM
} >RAM1

/* Uninitialized data section into "SRAM1" Ram type memory */
. = ALIGN(8);
Expand Down