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Capture simulator stdout and stderr streams to python side.#105

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chiplet wants to merge 3 commits into
v1.14_RCfrom
dev/vhirvone/capture-stdout-and-stderr
Draft

Capture simulator stdout and stderr streams to python side.#105
chiplet wants to merge 3 commits into
v1.14_RCfrom
dev/vhirvone/capture-stdout-and-stderr

Use right rtlcmd variable for specifying rtl simulation command

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