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Feature/add risc-v support#403

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zl523856 wants to merge 1 commit into
VectorCamp:developfrom
zte-riscv:vectorscan-rv
Open

Feature/add risc-v support#403
zl523856 wants to merge 1 commit into
VectorCamp:developfrom
zte-riscv:vectorscan-rv

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@zl523856

@zl523856 zl523856 commented Jul 9, 2026

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This pull request ports vectorscan to the RISC-V architecture. All test have been successfully verified and passed on RISC-V platforms.

./bin/unit-hyperscan results:
[----------] Global test environment tear-down
[==========] 3000 tests from 39 test cases ran. (3674830 ms total) [ PASSED ] 3000 tests.

./bin/unit-internal results:
[----------] Global test environment tear-down
[==========] 14162 tests from 81 test cases ran. (5733472 ms total) [ PASSED ] 14162 tests.

This pull request ports vectorscan to the RISC-V architecture. All test  have been successfully verified and passed on RISC-V platforms.

 ./bin/unit-hyperscan results:
[----------] Global test environment tear-down
[==========] 3000 tests from 39 test cases ran. (3674830 ms total)
[  PASSED  ] 3000 tests.

./bin/unit-internal results:
[----------] Global test environment tear-down
[==========] 14162 tests from 81 test cases ran. (5733472 ms total)
[  PASSED  ] 14162 tests.
@markos markos added the wishlist Something that would be nice to have but not a priority label Jul 9, 2026
@markos

markos commented Jul 9, 2026

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Hi @zl523856, thank you for the contribution. For now this will remain just a wishlist, I will not merge a PR for a platform that does not have hardware supported in the CI, I have some risc-v (BPI-F3) but it's so unbearably slow that it does not make sense to delay a merge until it gets compiled on RISC-V.
Finally, I will not merge a PR that I will have to maintain afterwards unless there is a support contract for that.

Now on the technical side, You seem to add Fat runtime support for RISC-V but what does this mean? There are also some typos eg in CMakeLists, where you seem to add neon_sources. I need to take a closer look for details.

In short, I appreciate your effort, but this will not get merged until the above issues are solved.

@zl523856

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technical side

Thank you for your candid feedback and for taking the time to review this PR. I completely understand your concerns regarding CI hardware limitations and the long-term maintenance burden.

Long-term maintenance: Our company is happy to provide long-term maintenance for the RISC-V platform in this repository. Do you have a template for the support contract you mentioned? Perhaps we could discuss this further via email — my address is zhou.lu1@zte.com.cn.

CI and build speed: To avoid impacting your workflow, I can take charge of the verification work. Before pushing, I will ensure that all benchmarks pass and provide the logs. Alternatively, you can propose any other validation steps you deem necessary.

Technical follow-up: I will complete the modifications, verify that everything passes, and push again.

Since this feature is highly significant for RISC-V users, I truly hope we can find a compromise to get it merged.

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