Add jagged_index_select_2d_forward XPU operator - #92
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Remove .gitkeep placeholders
- Add invert_permute kernel to CMake build - Implement invert_permute Python wrapper in ops.py - Register invert_permute operator with schema existence check - Add torch_library.h utility for schema validation
Add SYCL/XPU kernel implementation for invert_permute operation.
Add complete test coverage for invert_permute operator on XPU devices, covering correctness, validation, parity, and performance. Test coverage includes: - Correctness tests for int32/int64 with edge cases (empty, single element, identity, reverse, random permutations) - Input validation tests for invalid dimensions and dtypes - Meta function tests for torch.compile compatibility - PyTorch opcheck validation for operator conventions - Parametric tests with varying sizes (1 to 1M elements) - CPU-XPU parity tests to ensure consistent results - Performance benchmarks measuring execution time and bandwidth
- CMakeLists: add permute_1d_sparse_data.cpp to build sources - ops.py: add Python wrapper with type hints - ops_registry.cpp: register operator schema in fbgemm namespace
Implement SYCL/XPU kernel implementation of permute_1D_sparse_data operator for sparse jagged/1D format data permutation.
Replace the custom standalone test_invert_permute.py with a git-am patch applied to upstream FBGEMM v1.7.0 misc_ops_test.py, following the torchcodec-xpu convention. The patch makes test_invert_permute run on XPU (permute.xpu(), gated on torch.xpu.is_available()) and skips the remaining operator tests that are not implemented on XPU.
Collapse the two type-specific kernel functors (InvertPermuteKernelInt32, InvertPermuteKernelInt64) into a single templated functor InvertPermuteKernel<index_t>, mirroring the reference CUDA kernel invert_permute_kernel<index_t>.
Replaced test for upstream patched FBGEMM tests that enables testing XPU. This file is no longer needed.
Add SYCL port of FBGEMM's asynchronous_complete_cumsum operator for Intel XPU devices. The operator computes a complete cumulative sum with a leading zero (e.g., [a, b, c] → [0, a, a+b, a+b+c]).
Integrate asynchronous_complete_cumsum operator into fbgemm-xpu: - Add Python wrapper with complete cumsum documentation - Register operator schema in torch library - Include implementation in CMake build
Add comprehensive test suite for asynchronous_complete_cumsum operator covering: - Basic functionality with int32 and int64 dtypes - Empty tensor handling - Random input validation with numpy reference
Delete the accidentally tracked submodule reference to FBGEMM-v1.7.0.
Add SYCL infrastructure headers from intel/torch-xpu-ops/ to support advanced kernel implementations: - DeviceProperties.h: Device capability queries and work group sizing - SYCLContext.h: SYCL context management and namespace aliases - SYCLHelpers.h: SYCL kernel submission and utility functions - TensorInfo.h: Tensor metadata and dimension handling structures - TensorOptions.h: Tensor configuration and options management - Runtime.h: SYCL runtime utilities - Macros.h: Common macro definitions - Scalar.h: Scalar type conversion utilities These headers provide the foundation for implementing 2D sparse data permutation and other complex SYCL operations on XPU devices.
Add foundational utility headers and implementations to support complex SYCL kernel operations: - utils.h/cpp: Core constants, type definitions, kernel launch helpers, and device property queries - dispatch_macros.h: Type dispatch macros for handling multiple data types (int32, int64, float, etc.) - tensor_utils.h: Tensor manipulation and metadata utilities - function_types.h: Symbol visibility definitions for shared library exports These utilities provide essential infrastructure for implementing 2D sparse data permutation and other advanced operators on XPU devices, including work group sizing, kernel launch helpers, and type-safe dispatching mechanisms.
Add SYCL port of FBGEMM's permute_2D_sparse_data operator for Intel XPU devices. This operator permutes 2D sparse data including lengths [T, B], indices, and optional weights according to a permutation vector, commonly used for reordering embedding table features. Implementation includes: - SYCL kernels: permute_2D_lengths_kernel and permute_2D_data_kernel - Host function: permute_2D_sparse_data_xpu
Integrate permute_2D_sparse_data operator into fbgemm-xpu: - Add Python wrapper with type hints and documentation - Register operator schema in torch library - Include implementation files in CMake build (utils.cpp, SYCL kernels, and operator implementation)
Add comprehensive test suite for permute_2D_sparse_data operator covering: - Basic functionality with int32 and int64 data types - Sparse data with and without weights - Permutations with repeated indices - Exact value validation - CPU-XPU consistency verification
Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
The permute_2d_sparse_data_op.cpp file was incorrectly emptied. Restore the SYCL implementation.
flezaalv
changed the title
- Add packages/fbgemm-xpu/test/patches/0002-Add-XPU-support-to-fbgemm-tbe- training-tests.patch - The patch is independent of 0001-Add-XPU-support-to-fbgemm-tests.patch - Removed previous tests for lookup operators.
Integrate asynchronous_complete_cumsum operator into fbgemm-xpu: - Add Python wrapper with complete cumsum documentation - Register operator schema in torch library - Include implementation in CMake build
Integrate permute_2D_sparse_data operator into fbgemm-xpu: - Add Python wrapper with type hints and documentation - Register operator schema in torch library - Include implementation files in CMake build (utils.cpp, SYCL kernels, and operator implementation)
Fixes CMake configuration and import ordering to properly build and load the block_bucketize_sparse_features XPU operator. - Configure CMake for XPU-only PyTorch builds - Import torch before _C extension to load libtorch.so dependencies - Adjust test imports for consistency All 18 tests passing.
Register operator schemas and add Python bindings for split and dense embedding lookup functions. Changes span ops_registry.cpp and ops.py.
Add src/codegen/CMakeLists.txt to drive code generation and build the _C_training Python extension module, and wire it into the top-level build.
Implement reorder_batched_ad_lengths and reorder_batched_ad_indices operators with SYCL kernels for Intel XPU devices.
Add build system integration and Python API for reorder_batched_ad operators introduced in the previous commit.
Add comprehensive test suite for reorder_batched_ad_lengths and reorder_batched_ad_indices operators, covering both broadcast and non-broadcast modes.
Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
…ng standards Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
Integrate asynchronous_complete_cumsum operator into fbgemm-xpu: - Add Python wrapper with complete cumsum documentation - Register operator schema in torch library - Include implementation in CMake build
Integrate permute_2D_sparse_data operator into fbgemm-xpu: - Add Python wrapper with type hints and documentation - Register operator schema in torch library - Include implementation files in CMake build (utils.cpp, SYCL kernels, and operator implementation)
Fixes CMake configuration and import ordering to properly build and load the block_bucketize_sparse_features XPU operator. - Configure CMake for XPU-only PyTorch builds - Import torch before _C extension to load libtorch.so dependencies - Adjust test imports for consistency All 18 tests passing.
Register operator schemas and add Python bindings for split and dense embedding lookup functions. Changes span ops_registry.cpp and ops.py.
Add src/codegen/CMakeLists.txt to drive code generation and build the _C_training Python extension module, and wire it into the top-level build.
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Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
Signed-off-by: Felipe Leza Alvarez <felipe.leza.alvarez@intel.com>
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Added upstream FBGEMM test coverage for |
Update device selection order in the test patch to check for XPU
availability first, then fall back to CPU or CUDA. This ensures XPU
tests run on XPU hardware when available, rather than defaulting to
CPU even when XPU is present.
Changes the device logic from:
"cpu" if use_cpu else ("xpu" if xpu_available else "cuda")
to:
"xpu" if xpu_available else ("cpu" if use_cpu else "cuda")
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This commit introduces the
jagged_index_select_2d_forwardoperator for Intel XPU devices, enabling 2D index selection on jagged tensors with offset-based indexing.Depends on #87.
Changes
New SYCL Kernel Implementation (
jagged_index_select_2d.cpp/h)JaggedIndexSelect2dKernelfunctor for SYCL/XPU executionOperator Registration (
ops_registry.cpp)fbgemmnamespaceBuild Integration (
CMakeLists.txt)cc: @aagalleg, @manuelhsantana