Transpose/Test: Add support for compact transposition output matrices and a working verilator flow

[da-gazzi]

Compact Transposition and Verilator Testing

Summary

• Add optional compact storage for transposed output matrices while retaining
  the existing tile-padded layout.
• Make partial transpose tiles memory-safe without changing the number or
  ordering of generated tile requests.
• Add a reusable, parameterized Verilator flow and broaden the directed
  transpose and midend regression coverage.

Compact Transposition

• Add a software-configurable compact transpose option to the request and
  register interfaces.
• In compact mode, generate the destination row stride from the actual
  transposed row width. Legacy mode continues to use the tile-padded width.
• Add a request replay stage after ND expansion. Requests for inactive rows of
  partial edge tiles are redirected to the first valid source or destination
  address, preventing out-of-bounds reads and unsafe zero-strobe write
  addresses while preserving the descriptor sequence expected by the
  transpose engine.
• Clarify the transpose element-width and tile-geometry semantics in the RTL
  documentation.

Testbench Changes

• Cover compact and padded layouts, partial edge tiles, aligned and unaligned
  matrices, 1-, 2-, and 4-byte elements, multiple bus widths, backpressure,
  and back-to-back transfers.
• Check results against the DPI golden model and verify sentinel regions and
  generated write-address bounds.
• Exercise full- and half-duplex transpose configurations together with the
  ND, runtime, and register frontend midends.
• Use SystemVerilog clocking blocks for race-free ready/valid stimulus and
  handshake observation.

Verilator Flow

• Add common Verilator build and run plumbing with independent build
  directories for each testbench parametrization.
• Generate stable Bender file lists and track RTL sources, headers, DPI code,
  and elaboration options so binaries rebuild when their inputs change.
• Provide explicit per-testbench parameter matrices, convenient aggregate
  targets, clean targets, optional FST tracing, and configurable compiler and
  linker flags.
• Make the transpose DPI model link correctly when compiled as C++ by
  Verilator.

Validation

• The directed compact/padded transpose configurations, back-to-back tests,
  on-the-fly transpose variants, and affected midend tests pass with the new
  Verilator flow.

TODO

• This PR is based on top of Regs/Transpose: Add compute parameter register to register frontend and fix transpose to/from misaligned addresses #160 which in turn is based on previous PRs; those should be merged first
• The non-free gitlab CI does not pass - as I am not at IIS anymore, I can't see why, I will happily change whatever is needed to fix this.