Basic arch path

.gitignore

@@ -53,3 +53,4 @@ dkms.conf
 
 #Iverilog Simulation Files
 *.vcd
+*a.out

README.md

@@ -4,6 +4,30 @@ RISCV SoC Collab work.
 
 Join On [Discord](https://discord.gg/sQjhBvWXjF) if you interested in the project!
 
+# *UPDATE*
+
+Team has decided to change course. Implementation of a simpler core will begin.
+2 Cycle implementation in the works. RV32I. This is early development before we break
+it down into a 5 stage pipeline.
+
+
+---
+
+## Simulation instructions
+
+
+Setup environment variables.
+
+Run the following command inside the top directory of this project.
+```sh
+source setup.sh 
+```
+
+Run make command in sim directory to build simulation.
+```sh
+make
+```
+
 ---
 
 # General SoC Architecture idea

design/core.sv

@@ -1,13 +1,67 @@
-`include "core.pkg"
-
 module core
-  (
-    input clk,
-    input rst
-  );
-
-
-
-
+(
+    //Clock is shared with WB4 BUS
+    input logic clk,
+    input logic rst,
+
+
+    //Wishbone signals
+    output logic [31:0] addr_o,
+    input  logic [31:0] dat_i,
+    output logic [31:0] dat_o,
+
+    input  logic ack_i,
+    input  logic err_i,
+    output logic cyc_o,
+    output logic stb_o,
+    output logic we_o
+
+);
 
+typedef enum logic [1:0] { FETCH, EXECUTE } exec_state_t;
+
+exec_state_t current_state = FETCH;
+
+logic [64:0] IR = 0;
+
+wire [6:0]  funct7   = IR[31:25];
+wire [4:0]  rs2      = IR[24:20];
+wire [4:0]  rs1      = IR[19:15];
+wire [2:0]  funct3   = IR[14:12];
+wire [4:0]  rd       = IR[11:7];
+wire [6:0]  opcode   = IR[6:0];
+
+wire [11:0] imm      = IR[31:20];
+
+wire [6:0]  imm_11_5 = IR[31:25];
+wire [4:0]  imm_4_0  = IR[11:7];
+
+wire [19:0] imm_31_12 = IR[31:12];
+
+//Main state machine for the instruction execution cycle.
+always@(posedge clk)
+begin
+    case (current_state)
+    FETCH:;
+        //TODO: Implement Fetch From Wishbone 4 interface. Synchronous Mode.
+        //Illustration 4-2: WISHBONE Classic synchronous cycle terminated burst
+        //https://cdn.opencores.org/downloads/wbspec_b4.pdf
+        //Page: 66
+
+    EXECUTE:;
+        //TODO: Implement ALU Execution
+
+        //TODO: Implement Memory Write
+
+        //TODO: Implement Memory Reads
+
+        //TODO: Implement Branch Instructions
+
+        //NOTES: The state machine can have nested states to accommodate wishbone BUS logic.
+
+    default:;
+    endcase
+end
+
+
 endmodule

design/wb4_sram.sv

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: MIT
+
+/* ------------------------------------------------------------------------- */
+
+
+//TODO: Will need to redo defaults.
+// `include "defaults/defaults.sv"
+
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Module: Internal SRAM With Wishbone BUS
+ *
+ * Parameters:
+ *  num_words: Number of words in the memory (default = 4096).
+ *
+ */
+module wb4_sram #(
+    parameter num_words = 4096
+) (
+    input logic clk,
+    input logic rst,
+
+    // Wishbone signals
+    input  logic [31:0] addr_i,
+    input  logic [31:0] dat_i,
+    output logic [31:0] dat_o,
+
+    output logic ack_o,
+    output logic err_o,
+    input logic cyc_i,
+    input logic stb_i,
+    input logic we_i
+);
+    reg [31:0] memory [0:(num_words - 1)];
+
+    // For address calculation
+    localparam ADDR_WIDTH = $clog2(num_words);
+    wire [ADDR_WIDTH-1:0] word_addr;
+    wire addr_valid;
+
+    initial begin
+        $readmemh("../firmware/crt0.hex", memory);
+    end
+
+    assign word_addr = addr_i[ADDR_WIDTH+1:2]; // Byte to word address
+    assign addr_valid = (addr_i[31:ADDR_WIDTH+2] == 0); // Check upper bits are 0
+
+    always @(posedge clk) begin
+        if (rst)
+        begin
+            ack_o <= 1'b0;
+            err_o <= 1'b0;
+            dat_o <= 32'b0;
+        end 
+        else
+        begin
+            if (cyc_i && stb_i) begin
+                if (addr_valid) begin
+                    if (we_i)
+                    begin
+                        memory[word_addr] <= dat_i;
+                    end
+                    else
+                    begin
+                        dat_o <= memory[word_addr];
+                    end
+                    ack_o <= 1'b1;
+                    err_o <= 1'b0;
+                end 
+                else
+                begin
+                    ack_o <= 1'b0;
+                    err_o <= 1'b1;
+                end
+            end 
+            else
+            begin
+                ack_o <= 1'b0;
+                err_o <= 1'b0;
+            end
+        end
+    end
+endmodule
+
+/* ------------------------------------------------------------------------- */
+
+
+/* End of file. */

firmware/Makefile

@@ -0,0 +1,7 @@
+
+
+all:
+	riscv64-unknown-elf-as -march=rv64i -mabi=lp64 crt0.s -o crt0.o
+	riscv64-unknown-elf-ld -Ttext=0x0 -o crt0.elf crt0.o
+	riscv64-unknown-elf-objdump -d crt0.elf
+	riscv64-unknown-elf-objcopy -O verilog --verilog-data-width=4 crt0.elf crt0.hex

firmware/crt0.s

@@ -0,0 +1,13 @@
+    .section .text
+    .globl _start
+
+_start:
+    addi x1, x0, 5      # x1 = 5
+    addi x2, x0, 3      # x2 = 3
+    add  x3, x1, x2     # x3 = 8
+    sd   x3, 0(x0)      # mem[0] = 8
+    li   x4, 4          # x4 = 4
+loop:
+    addi x4, x4, -1     # x4--
+    bnez x4, loop       # branch until x4 == 0
+    ebreak              # done

setup.sh

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: MIT
+
+export CORE_REPO_PATH=$(pwd)

sim/Makefile

@@ -1,31 +1,16 @@
 
-TOPFILE ?= $(CORE_REPO_PATH)/sim/top.sv
-DSFILE ?= $(CORE_REPO_PATH)/design/core.sv
-TBFILE ?= $(CORE_REPO_PATH)/testbench/tb.sv
 
-all:
-	iverilog \
-	-g 2012 \
-	-g relative-include \
-	-c $(CORE_REPO_PATH)/sim/top.filelist \
-	$(TOPFILE);
-	./a.out;
 
-core:
-	iverilog \
-	-g 2012 \
-	-g relative-include \
-	-c $(CORE_REPO_PATH)/design/core.filelist \
-	$(DSFILE);
-	./a.out;
+#############
 
-tb:
-	iverilog \
-	-g 2012 \
-	-g relative-include \
-	-c $(CORE_REPO_PATH)/testbench/tb.filelist \
-	$(TBFILE);
-	./a.out;
+DESIGN = ../design
+TESTBENCH = ../testbench
+RTL_FILES = $(DESIGN)/wb4_sram.sv $(DESIGN)/core.sv
+
+SOC_TEST_BENCH = $(RTL_FILES) $(TESTBENCH)/tb.sv
+
+all: $(SOC_TEST_BENCH)
+	iverilog $(SOC_TEST_BENCH) -g2012
 
 clean:
 	rm -rf *.out *.vcd *.log;