FEDP2K + WGMMA dse + opts #380
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,22 +1,42 @@ | ||
| { | ||
| "tensor_wg:perf_gate-wgmma-fp16-ss:rtlsim": { | ||
| "32": { | ||
| "cycles": 107212, | ||
| "instrs": 66640 | ||
| }, | ||
| "app": "sgemm_tcu_wg", | ||
| "args": "-m 64 -n 64 -k 64", | ||
| "config_hash": "64856bfe7975f530", | ||
| "configs": "-DVX_CFG_NUM_THREADS=8 -DVX_CFG_NUM_WARPS=8 -DVX_CFG_ISSUE_WIDTH=4 -DVX_CFG_EXT_TCU_ENABLE -DVX_CFG_TCU_WGMMA_ENABLE -DITYPE=fp16 -DOTYPE=fp32 -DWGMMA_NRC=32 -DWGMMA_SS" | ||
| }, | ||
| "tensor_wg:perf_gate-wgmma-fedp2k-rs:rtlsim": { | ||
| "32": { | ||
| "cycles": 166490, | ||
| "instrs": 108512 | ||
| }, | ||
| "app": "sgemm_tcu_wg", | ||
| "args": "-m64 -n64 -k64", | ||
| "config_hash": "84f3ab0ee89d1c7e", | ||
| "configs": "-DVX_CFG_NUM_THREADS=8 -DVX_CFG_NUM_WARPS=8 -DVX_CFG_ISSUE_WIDTH=4 -DVX_CFG_EXT_TCU_ENABLE -DVX_CFG_TCU_WGMMA_ENABLE -DVX_CFG_TCU_FEDP2K -DITYPE=fp16 -DOTYPE=fp32 -DWGMMA_NRC=8 -DWGMMA_RS" | ||
| }, | ||
| "tensor_wg:perf_gate-wgmma-sp-rs:rtlsim": { | ||
| "32": { | ||
| "cycles": 778048, | ||
| "instrs": 438752 | ||
| }, | ||
| "app": "sgemm_tcu_wg_sp", | ||
| "args": "-m 128 -n 128 -k 128", | ||
| "config_hash": "6524c99e95160ff1", | ||
| "configs": "-DVX_CFG_NUM_THREADS=8 -DVX_CFG_NUM_WARPS=8 -DVX_CFG_ISSUE_WIDTH=4 -DVX_CFG_EXT_TCU_ENABLE -DVX_CFG_TCU_WGMMA_ENABLE -DVX_CFG_TCU_SPARSE_ENABLE -DWGMMA_NRC=32 -DWGMMA_RS" | ||
| }, | ||
| "tensor_wg:perf_gate-wgmma-mx-fedp2k-rs:rtlsim": { | ||
| "32": { | ||
| "cycles": 139877, | ||
| "instrs": 86304 | ||
| }, | ||
| "app": "sgemm_tcu_wg_mx", | ||
| "args": "-m64 -n64 -k64", | ||
| "config_hash": "a0d52f0bb1cc7294", | ||
| "configs": "-DVX_CFG_NUM_THREADS=8 -DVX_CFG_NUM_WARPS=8 -DVX_CFG_ISSUE_WIDTH=4 -DVX_CFG_EXT_TCU_ENABLE -DVX_CFG_TCU_WGMMA_ENABLE -DVX_CFG_TCU_MX_ENABLE -DVX_CFG_TCU_FP8_ENABLE -DVX_CFG_TCU_FEDP2K -DVX_CFG_TCU_TYPE_DPI -DITYPE=mxfp8 -DOTYPE=fp32 -DWGMMA_NRC=8 -DWGMMA_RS" | ||
| } | ||
| } | ||
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Do not modify the coverage of an existing baseline; we need to have perfect args and config match to catch regression.
You are free to expand the perf gate coverage with new tests
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this test was defaulting to RS mode previously (from sgemm_tcu_wg makefile)
so we were essentially never testing SS mode in perf_gate
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and I also changed 128^3 to 64^3 cause large rtlsim runs would just crash verilator on my local setup
so I couldnt even generate the SS baseline with 128^3
but i guess if we really want large dims for this I can fail this particular perf_gate test once in CI on purpose and then get the value from there and then manually edit baseline instead of through pytest?