Regs/Transpose: Add compute parameter register to register frontend and fix transpose to/from misaligned addresses - #160
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- This target generates C headers in `target/sw` with both the `raw-header` and `c-header` PeakRDL plugins - Also added to `deploy` CI job
- the PeakRDL `c-header` plugin generates structs with `__attribute__((__packed__))` which ensures proper packing of fields but can also cause the compiler to emit byte loads/stores to access 32-bit registers, which is definitely not what we want. The `unpacked` version of the C header has the attribute removed. - The `idma_sw_clean` target had a typo and didn't actually clean anything, this is fixed now.
- Replace `enable_compute` in backend generation with a SystemVerilog parameter - Add `EnableCompute`, `ComputeOps`, and `ComputeFullDuplex` parameters to eligible backend, synthesis wrapper, and transport-layer modules. - Omit compute parameters entirely for generated topologies that cannot support the compute datapath - Keep the non-compute path available in compute-capable variants with `EnableCompute = 0`, and instantiate `idma_otf_compute` only when enabled. - Remove `IDMA_VIDMA_IDS` / `--compute-ids` plumbing from the generator and makefile; compute support is now selected at elaboration. - Update transpose testbenches to enable compute explicitly and keep the inst64 frontend backend instantiation compute-disabled
- `compute_cfg` register is added after existing registers - Controls `enable`, `op`, `mode`, `tensor_m` and `tensor_n` - Connected to the relevant fields of the ND request struct in the register top-level template - Add required additional frontend IDs to CI deploy job
- With misaligned destination addresses, 2 write beats may be required to write a single row of the transpose buffer. - The `ready_i` signal should thus be asserted only when the entire transaction is done (`w_dp_req_ready` asserted), not when a single write beat is done.
da-gazzi
requested review from
DanielKellerM,
micprog and
thommythomaso
as code owners
July 20, 2026 09:51
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Merge order:
This PR is based on the PR making the compute engine instantiation an elaboration-time parameter instead of a generation-time one, see #159 - that PR should be merged before this one.
Changes:
deployjob (IDMA_ADD_FE_IDS)ready_itow_dp_req_readyinstead ofwrite_beat_done; that signal is asserted on the last transaction of a write transfer, which is the correct behavior.