A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
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Updated
Nov 7, 2021 - C++
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top Pick for 2020.
Store, search, and reason over data in spike timing — spiking neural networks for data storage & retrieval. Less compute, less storage. Three paradigms: telemetry hub, in-storage query engine, relational spike-time embeddings.
Temporal Coding as a Substrate for Sensorimotor Object Inference: A Spiking Reinterpretation of Thousand Brains Architecture
A biologically-inspired time-delay neural network that learns transmission delays for speech and temporal pattern recognition (NYAS 2016).
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